Modifications for 0.8.1:
======================================================================
+* Added "echo" command
+
+* Added "tags" make target
+
+* Fix serial driver for MPC8xx / SCC
+
+* Fix compile problems with cogent_mpc8xx
+
+* Use macros with arguments instead of lots of separate #defines in
+ the cogent/hymod flash drivers
+
* Add configuration for Walnut405 (Anne-Sophie Harnois)
* Fix bug in PCMCIA initialization; add PCMCIA support for IVML24
#########################################################################
+tags:
+ ctags -w `find $(SUBDIRS) include \
+ \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
+
clean:
rm -f `find . -type f \
\( -name 'core' -o -name '*.bak' \
rm -f `find . -type f \
\( -name .depend -o -name '*.srec' -o -name '*.bin' \) \
-print`
- rm -f $(OBJS) *.bak
+ rm -f $(OBJS) *.bak tags
rm -fr *.*~
rm -f ppcboot ppcboot.bin ppcboot.elf ppcboot.srec ppcboot.map
return 2;
#ifdef FLASH_DEBUG
- printf("\nMaster Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFGM(addr));
- printf("Block 0 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG0(addr));
- printf("Block 1 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG1(addr));
- printf("Block 2 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG2(addr));
- printf("Block 3 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG3(addr));
- printf("Block 4 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG4(addr));
- printf("Block 5 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG5(addr));
- printf("Block 6 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG6(addr));
- printf("Block 7 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG7(addr));
- printf("Block 8 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG8(addr));
- printf("Block 9 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG9(addr));
- printf("Block 10 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG10(addr));
- printf("Block 11 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG11(addr));
- printf("Block 12 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG12(addr));
- printf("Block 13 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG13(addr));
- printf("Block 14 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG14(addr));
- printf("Block 15 Lock Config = 0x%08lx\n", *C302F_BNK_ADDR_CFG15(addr));
+ {
+ int i;
+
+ printf("\nMaster Lock Config = 0x%08lx\n",
+ *C302F_BNK_ADDR_CFGM(addr));
+ for (i = 0; i < C302F_BNK_NBLOCKS; i++)
+ printf("Block %2d Lock Config = 0x%08lx\n",
+ i, *C302F_BNK_ADDR_CFG(i, addr));
+ }
#endif
/* reset the flash again */
#define I8S5_ADDR_MAN 0x00000 /* manufacturer's id */
#define I8S5_ADDR_DEV 0x00001 /* device id */
#define I8S5_ADDR_CFGM 0x00003 /* master lock configuration */
-#define I8S5_ADDR_CFG0 0x00002 /* block lock configuration */
-#define I8S5_ADDR_CFG1 0x10002 /* " */
-#define I8S5_ADDR_CFG2 0x20002 /* " */
-#define I8S5_ADDR_CFG3 0x30002 /* " */
-#define I8S5_ADDR_CFG4 0x40002 /* " */
-#define I8S5_ADDR_CFG5 0x50002 /* " */
-#define I8S5_ADDR_CFG6 0x60002 /* " */
-#define I8S5_ADDR_CFG7 0x70002 /* " */
-#define I8S5_ADDR_CFG8 0x80002 /* " */
-#define I8S5_ADDR_CFG9 0x90002 /* " */
-#define I8S5_ADDR_CFG10 0xA0002 /* " */
-#define I8S5_ADDR_CFG11 0xB0002 /* " */
-#define I8S5_ADDR_CFG12 0xC0002 /* " */
-#define I8S5_ADDR_CFG13 0xD0002 /* " */
-#define I8S5_ADDR_CFG14 0xE0002 /* " */
-#define I8S5_ADDR_CFG15 0xF0002 /* " */
+#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */
/* Commands */
#define I8S5_CMD_RST 0xFF /* reset flash */
#define C302F_BNK_ADDR_MAN(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN)
#define C302F_BNK_ADDR_DEV(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV)
#define C302F_BNK_ADDR_CFGM(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM)
-#define C302F_BNK_ADDR_CFG0(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG0)
-#define C302F_BNK_ADDR_CFG1(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG1)
-#define C302F_BNK_ADDR_CFG2(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG2)
-#define C302F_BNK_ADDR_CFG3(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG3)
-#define C302F_BNK_ADDR_CFG4(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG4)
-#define C302F_BNK_ADDR_CFG5(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG5)
-#define C302F_BNK_ADDR_CFG6(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG6)
-#define C302F_BNK_ADDR_CFG7(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG7)
-#define C302F_BNK_ADDR_CFG8(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG8)
-#define C302F_BNK_ADDR_CFG9(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG9)
-#define C302F_BNK_ADDR_CFG10(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG10)
-#define C302F_BNK_ADDR_CFG11(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG11)
-#define C302F_BNK_ADDR_CFG12(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG12)
-#define C302F_BNK_ADDR_CFG13(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG13)
-#define C302F_BNK_ADDR_CFG14(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG14)
-#define C302F_BNK_ADDR_CFG15(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG15)
+#define C302F_BNK_ADDR_CFG(b,a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b))
/*
* replicate a chip cmd/stat/rd value into each byte position within a word
#define CMBF_BNK_ADDR_MAN(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN)
#define CMBF_BNK_ADDR_DEV(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV)
#define CMBF_BNK_ADDR_CFGM(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM)
-#define CMBF_BNK_ADDR_CFG0(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG0)
-#define CMBF_BNK_ADDR_CFG1(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG1)
-#define CMBF_BNK_ADDR_CFG2(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG2)
-#define CMBF_BNK_ADDR_CFG3(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG3)
-#define CMBF_BNK_ADDR_CFG4(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG4)
-#define CMBF_BNK_ADDR_CFG5(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG5)
-#define CMBF_BNK_ADDR_CFG6(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG6)
-#define CMBF_BNK_ADDR_CFG7(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG7)
-#define CMBF_BNK_ADDR_CFG8(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG8)
-#define CMBF_BNK_ADDR_CFG9(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG9)
-#define CMBF_BNK_ADDR_CFG10(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG10)
-#define CMBF_BNK_ADDR_CFG11(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG11)
-#define CMBF_BNK_ADDR_CFG12(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG12)
-#define CMBF_BNK_ADDR_CFG13(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG13)
-#define CMBF_BNK_ADDR_CFG14(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG14)
-#define CMBF_BNK_ADDR_CFG15(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG15)
+#define CMBF_BNK_ADDR_CFG(b,a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b))
/*
* replicate a chip cmd/stat/rd value into each byte position within a word
#include <ppcboot.h>
#include <board/cogent/serial.h>
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) && \
- ((defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
- (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE)))
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+
+#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
+ (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
#if CONFIG_CONS_INDEX == 1
#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE
return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0);
}
-#endif
+#endif /* CONS_NONE */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && \
- (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) && \
defined(CONFIG_KGDB_NONE)
+#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
+#error Console and kgdb are on the same serial port - this is not supported
+#endif
+
#if CONFIG_KGDB_INDEX == 1
#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALA_BASE
#elif CONFIG_KGDB_INDEX == 2
}
}
-#endif
+#endif /* KGDB && KGDB_NONE */
+
+#endif /* CAPS & SERPAR */
/* register addresses, valid only following an CHIP_CMD_RD_ID command */
#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
-#define CHIP_ADDR_REG_CFG0 0x000002 /* lock config for block 0 */
#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
-#define CHIP_ADDR_REG_CFG1 0x010002 /* lock config for block 1 */
-#define CHIP_ADDR_REG_CFG2 0x020002 /* lock config for block 2 */
-#define CHIP_ADDR_REG_CFG3 0x030002 /* lock config for block 3 */
-#define CHIP_ADDR_REG_CFG4 0x040002 /* lock config for block 4 */
-#define CHIP_ADDR_REG_CFG5 0x050002 /* lock config for block 5 */
-#define CHIP_ADDR_REG_CFG6 0x060002 /* lock config for block 6 */
-#define CHIP_ADDR_REG_CFG7 0x070002 /* lock config for block 7 */
-#define CHIP_ADDR_REG_CFG8 0x080002 /* lock config for block 8 */
-#define CHIP_ADDR_REG_CFG9 0x090002 /* lock config for block 9 */
-#define CHIP_ADDR_REG_CFG10 0x0A0002 /* lock config for block 10 */
-#define CHIP_ADDR_REG_CFG11 0x0B0002 /* lock config for block 11 */
-#define CHIP_ADDR_REG_CFG12 0x0C0002 /* lock config for block 12 */
-#define CHIP_ADDR_REG_CFG13 0x0D0002 /* lock config for block 13 */
-#define CHIP_ADDR_REG_CFG14 0x0E0002 /* lock config for block 14 */
-#define CHIP_ADDR_REG_CFG15 0x0F0002 /* lock config for block 15 */
-#define CHIP_ADDR_REG_CFG16 0x100002 /* lock config for block 16 */
-#define CHIP_ADDR_REG_CFG17 0x110002 /* lock config for block 17 */
-#define CHIP_ADDR_REG_CFG18 0x120002 /* lock config for block 18 */
-#define CHIP_ADDR_REG_CFG19 0x130002 /* lock config for block 19 */
-#define CHIP_ADDR_REG_CFG20 0x140002 /* lock config for block 20 */
-#define CHIP_ADDR_REG_CFG21 0x150002 /* lock config for block 21 */
-#define CHIP_ADDR_REG_CFG22 0x160002 /* lock config for block 22 */
-#define CHIP_ADDR_REG_CFG23 0x170002 /* lock config for block 23 */
-#define CHIP_ADDR_REG_CFG24 0x180002 /* lock config for block 24 */
-#define CHIP_ADDR_REG_CFG25 0x190002 /* lock config for block 25 */
-#define CHIP_ADDR_REG_CFG26 0x1A0002 /* lock config for block 26 */
-#define CHIP_ADDR_REG_CFG27 0x1B0002 /* lock config for block 27 */
-#define CHIP_ADDR_REG_CFG28 0x1C0002 /* lock config for block 28 */
-#define CHIP_ADDR_REG_CFG29 0x1D0002 /* lock config for block 29 */
-#define CHIP_ADDR_REG_CFG30 0x1E0002 /* lock config for block 30 */
-#define CHIP_ADDR_REG_CFG31 0x1F0002 /* lock config for block 31 */
+#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
/* Commands */
#define CHIP_CMD_RST 0xFF /* reset flash */
#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG0(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG0)
-#define BANK_ADDR_REG_CFG1(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG1)
-#define BANK_ADDR_REG_CFG2(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG2)
-#define BANK_ADDR_REG_CFG3(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG3)
-#define BANK_ADDR_REG_CFG4(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG4)
-#define BANK_ADDR_REG_CFG5(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG5)
-#define BANK_ADDR_REG_CFG6(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG6)
-#define BANK_ADDR_REG_CFG7(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG7)
-#define BANK_ADDR_REG_CFG8(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG8)
-#define BANK_ADDR_REG_CFG9(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG9)
-#define BANK_ADDR_REG_CFG10(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG10)
-#define BANK_ADDR_REG_CFG11(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG11)
-#define BANK_ADDR_REG_CFG12(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG12)
-#define BANK_ADDR_REG_CFG13(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG13)
-#define BANK_ADDR_REG_CFG14(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG14)
-#define BANK_ADDR_REG_CFG15(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG15)
-#define BANK_ADDR_REG_CFG16(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG16)
-#define BANK_ADDR_REG_CFG17(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG17)
-#define BANK_ADDR_REG_CFG18(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG18)
-#define BANK_ADDR_REG_CFG19(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG19)
-#define BANK_ADDR_REG_CFG20(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG20)
-#define BANK_ADDR_REG_CFG21(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG21)
-#define BANK_ADDR_REG_CFG22(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG22)
-#define BANK_ADDR_REG_CFG23(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG23)
-#define BANK_ADDR_REG_CFG24(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG24)
-#define BANK_ADDR_REG_CFG25(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG25)
-#define BANK_ADDR_REG_CFG26(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG26)
-#define BANK_ADDR_REG_CFG27(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG27)
-#define BANK_ADDR_REG_CFG28(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG28)
-#define BANK_ADDR_REG_CFG29(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG29)
-#define BANK_ADDR_REG_CFG30(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG30)
-#define BANK_ADDR_REG_CFG31(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG31)
+#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
/*
* replicate a chip cmd/stat/rd value into each byte position within a word
eeprom_init ();
eeprom_write(off, (uchar *)addr, cnt);
- printf ("done\n");
printf ("done\n");
return;
} else {
NULL \
),
+#define CMD_TBL_ECHO MK_CMD_TBL_ENTRY( \
+ "echo", 4, CFG_MAXARGS, 1, do_echo, \
+ "echo - echo args to console\n", \
+ "[args..]\n" \
+ " - echo args to console; \\c suppresses newline\n" \
+ ),
+
void
do_version (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
printf ("\n%s\n", version_string);
}
+void
+do_echo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ int i, putnl = 1;
+
+ for (i = 1; i < argc; i++) {
+ char *p = argv[i], c;
+
+ if (i > 1)
+ putc(' ');
+ while ((c = *p++) != '\0')
+ if (c == '\\' && *p == 'c') {
+ putnl = 0;
+ p++;
+ }
+ else
+ putc(c);
+ }
+
+ if (putnl)
+ putc('\n');
+}
+
/*
* Use puts() instead of printf() to avoid printf buffer overflow
* for long help messages
CMD_TBL_DCACHE
CMD_TBL_RESET
CMD_TBL_KGDB
+ CMD_TBL_ECHO
CMD_TBL_VERS
CMD_TBL_HELP
CMD_TBL_QUES
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
volatile cpm8xx_t *cp = &(im->im_cpm);
- uint dpaddr, dpsize, size;
+ uint dpaddr;
volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
/* initialize pointers to SCC */
/* Allocate space for two buffer descriptors in the DP ram.
*/
- dpaddr = CPM_DATAONLY_BASE;
- dpsize = CPM_DATAONLY_SIZE;
+#ifdef CFG_ALLOC_DPRAM
+ dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+#else
+ dpaddr = CPM_SERIAL_BASE ;
+#endif
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
up->scc_genscc.scc_rfcr = SCC_EB;
up->scc_genscc.scc_tfcr = SCC_EB;
- /* Updating dpram address and size
- */
- size = ((sizeof(cbd_t)*2 + 2) + 15) & ~15;
- dpaddr += size;
- dpsize -= size;
-
- /* Initialize CPM
- */
- m8xx_cpm_init(dpaddr, dpsize);
-
/* Set SCC(x) clock mode to 16x
* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
- sta_reg = sta_reg | (PHY_ADDR << 5); /* Phy address */
+ sta_reg = sta_reg | (CONFIG_PHY_ADDR << 5); /* Phy address */
out32(EMAC_STACR, sta_reg);
#if 0 /* test-only */
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
- sta_reg = sta_reg | ((unsigned long)PHY_ADDR << 5); /* Phy address */
+ sta_reg = sta_reg | ((unsigned long)CONFIG_PHY_ADDR << 5); /* Phy address */
memcpy(&sta_reg, &value,2); /* put in data */
out32(EMAC_STACR, sta_reg);
#define CFG_CMD_EEPROM 0x00010000 /* EEPROM read/write support */
#define CFG_CMD_ASKENV 0x00020000 /* ask for env variable */
#define CFG_CMD_RUN 0x00040000 /* run command in env variable */
+#define CFG_CMD_ECHO 0x00080000 /* echo arguments */
#define CFG_CMD_ALL 0xFFFFFFFF /* ALL commands */
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_EEPROM | \
- CFG_CMD_ASKENV )
+ CFG_CMD_ASKENV | \
+ CFG_CMD_ECHO )
/* Default configuration
*/
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) /* no network on ADCIOP */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#undef CONFIG_PCI_PNP /* no pci plug-and-play */
+#undef CONFIG_PCI_PNP /* no pci plug-and-play */
+
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IRQ) & ~CFG_CMD_NET)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#if 1
#define CONFIG_COMMANDS \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_ETHADDR 00:D0:93:00:05:B5
-
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+
+#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB)
#define CONFIG_BOOTARGS "root=/dev/ram rw"
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
+#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
+#define CONFIG_KGDB_NONE /* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
#define HALF 22
#define FULL 44
-#define PHY_ADDR 0x0001 /*0x0000*/ /* verify jumpers are correct */
-
/* phy register offsets */
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
projects / users / rw / ppcboot.git / commitdiff