dt-bindings: clock: Add indices for Exynos7885 TREX clocks

TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic
Shaper) inside the Exynos7885 SoC, and are needed for the SoC to
function correctly.

Add indices for these clocks.

Signed-off-by: David Virag <virag.david003@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220601233743.56317-3-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
index d2e1483f93e4ee10abed606712a17fdbecebc715..8256e7430b63d59a3df6176760c5311801500a7a 100644 (file)
--- a/include/dt-bindings/clock/exynos7885.h
+++ b/include/dt-bindings/clock/exynos7885.h
@@ -72,14 +72,21 @@
 #define TOP_NR_CLK                     61
 
 /* CMU_CORE */
-#define CLK_MOUT_CORE_BUS_USER         1
-#define CLK_MOUT_CORE_CCI_USER         2
-#define CLK_MOUT_CORE_G3D_USER         3
-#define CLK_MOUT_CORE_GIC              4
-#define CLK_DOUT_CORE_BUSP             5
-#define CLK_GOUT_CCI_ACLK              6
-#define CLK_GOUT_GIC400_CLK            7
-#define CORE_NR_CLK                    8
+#define CLK_MOUT_CORE_BUS_USER                 1
+#define CLK_MOUT_CORE_CCI_USER                 2
+#define CLK_MOUT_CORE_G3D_USER                 3
+#define CLK_MOUT_CORE_GIC                      4
+#define CLK_DOUT_CORE_BUSP                     5
+#define CLK_GOUT_CCI_ACLK                      6
+#define CLK_GOUT_GIC400_CLK                    7
+#define CLK_GOUT_TREX_D_CORE_ACLK              8
+#define CLK_GOUT_TREX_D_CORE_GCLK              9
+#define CLK_GOUT_TREX_D_CORE_PCLK              10
+#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE       11
+#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE       12
+#define CLK_GOUT_TREX_P_CORE_PCLK              13
+#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE       14
+#define CORE_NR_CLK                            15
 
 /* CMU_PERI */
 #define CLK_MOUT_PERI_BUS_USER         1