return count;
 }
 
-int __kvm_apic_update_irr(u32 *pir, void *regs)
+bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 {
        u32 i, vec;
-       u32 pir_val, irr_val;
-       int max_irr = -1;
+       u32 pir_val, irr_val, prev_irr_val;
+       int max_updated_irr;
+
+       max_updated_irr = -1;
+       *max_irr = -1;
 
        for (i = vec = 0; i <= 7; i++, vec += 32) {
                pir_val = READ_ONCE(pir[i]);
                irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
                if (pir_val) {
+                       prev_irr_val = irr_val;
                        irr_val |= xchg(&pir[i], 0);
                        *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
+                       if (prev_irr_val != irr_val) {
+                               max_updated_irr =
+                                       __fls(irr_val ^ prev_irr_val) + vec;
+                       }
                }
                if (irr_val)
-                       max_irr = __fls(irr_val) + vec;
+                       *max_irr = __fls(irr_val) + vec;
        }
 
-       return max_irr;
+       return ((max_updated_irr != -1) &&
+               (max_updated_irr == *max_irr));
 }
 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 
-int kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
+bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 {
        struct kvm_lapic *apic = vcpu->arch.apic;
 
-       return __kvm_apic_update_irr(pir, apic->regs);
+       return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 }
 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 
 
 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
                           int short_hand, unsigned int dest, int dest_mode);
 
-int __kvm_apic_update_irr(u32 *pir, void *regs);
-int kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
+bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
+bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
                     struct dest_map *dest_map);
 
        max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
        if (max_irr != 256) {
                vapic_page = kmap(vmx->nested.virtual_apic_page);
-               __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
+               __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
+                       vapic_page, &max_irr);
                kunmap(vmx->nested.virtual_apic_page);
 
                status = vmcs_read16(GUEST_INTR_STATUS);
                 * But on x86 this is just a compiler barrier anyway.
                 */
                smp_mb__after_atomic();
-               max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
+               kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
        } else {
                max_irr = kvm_lapic_find_highest_irr(vcpu);
        }