clk: sunxi-ng: a523: Add support for bus clocks

Add the basic bus clocks for the Allwinner A523 and T527 SoCs.
This covers the AHB, APB0 and APB1 clocks. Linux is not supposed to
change those clocks, but they are needed as parents for many other mod
clocks.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-7-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
index 455bca0c344bc4516339da69188a10619f72c8bb..c8a96b642bb1e9de2298374aefc63a2aab9d7462 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
@@ -331,6 +331,39 @@ static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x",
 static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x",
                           &pll_npu_4x_clk.common.hw, 4, 1, 0);
 
+
+/**************************************************************************
+ *                           bus clocks                                   *
+ **************************************************************************/
+
+static const struct clk_parent_data ahb_apb0_parents[] = {
+       { .fw_name = "hosc" },
+       { .fw_name = "losc" },
+       { .fw_name = "iosc" },
+       { .hw = &pll_periph0_600M_clk.hw },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb0_parents, 0x510,
+                                0, 5,          /* M */
+                                24, 2,         /* mux */
+                                0);
+static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb0_parents, 0x520,
+                                0, 5,          /* M */
+                                24, 2, /* mux */
+                                0);
+
+static const struct clk_parent_data apb1_parents[] = {
+       { .fw_name = "hosc" },
+       { .fw_name = "losc" },
+       { .fw_name = "iosc" },
+       { .hw = &pll_periph0_600M_clk.hw },
+       { .hw = &pll_periph0_480M_clk.common.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524,
+                                0, 5,          /* M */
+                                24, 3,         /* mux */
+                                0);
+
 /*
  * Contains all clocks that are controlled by a hardware register. They
  * have a (sunxi) .common member, which needs to be initialised by the common
@@ -358,6 +391,9 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
        &pll_ve_clk.common,
        &pll_audio0_4x_clk.common,
        &pll_npu_4x_clk.common,
+       &ahb_clk.common,
+       &apb0_clk.common,
+       &apb1_clk.common,
 };
 
 static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
@@ -403,6 +439,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
                [CLK_PLL_NPU_4X]        = &pll_npu_4x_clk.common.hw,
                [CLK_PLL_NPU_2X]        = &pll_npu_2x_clk.hw,
                [CLK_PLL_NPU]           = &pll_npu_1x_clk.hw,
+               [CLK_AHB]               = &ahb_clk.common.hw,
+               [CLK_APB0]              = &apb0_clk.common.hw,
+               [CLK_APB1]              = &apb1_clk.common.hw,
        },
 };