drm/amd/display: separate FEC capability from fec debug flag

[why]
FEC capability query should not be affected by debugging decision on
whether to disable FEC. We should not determine if display supports FEC
by checking debug option.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 4837640530ad293ada1f5bc27bbb95d7305a6c43..cc1b52b72c0bae05380cd6c6ac764bff5b7a14fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -207,7 +207,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
 
        if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
                                   dsc_caps, NULL,
-                                  &dc_sink->sink_dsc_caps.dsc_dec_caps))
+                                  &dc_sink->dsc_caps.dsc_dec_caps))
                return false;
 
        return true;
@@ -262,8 +262,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
                        if (!validate_dsc_caps_on_connector(aconnector))
-                               memset(&aconnector->dc_sink->sink_dsc_caps,
-                                      0, sizeof(aconnector->dc_sink->sink_dsc_caps));
+                               memset(&aconnector->dc_sink->dsc_caps,
+                                      0, sizeof(aconnector->dc_sink->dsc_caps));
 #endif
                }
        }
@@ -550,7 +550,7 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
                memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
                if (vars[i].dsc_enabled && dc_dsc_compute_config(
                                        params[i].sink->ctx->dc->res_pool->dscs[0],
-                                       &params[i].sink->sink_dsc_caps.dsc_dec_caps,
+                                       &params[i].sink->dsc_caps.dsc_dec_caps,
                                        params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
                                        0,
                                        params[i].timing,
@@ -571,7 +571,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
        kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
        dc_dsc_compute_config(
                        param.sink->ctx->dc->res_pool->dscs[0],
-                       &param.sink->sink_dsc_caps.dsc_dec_caps,
+                       &param.sink->dsc_caps.dsc_dec_caps,
                        param.sink->ctx->dc->debug.dsc_min_slice_height_override,
                        (int) kbps, param.timing, &dsc_config);
 
@@ -768,14 +768,14 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
                params[count].sink = stream->sink;
                aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
                params[count].port = aconnector->port;
-               params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
+               params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
                dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
                if (!dc_dsc_compute_bandwidth_range(
                                stream->sink->ctx->dc->res_pool->dscs[0],
                                stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
                                dsc_policy.min_target_bpp,
                                dsc_policy.max_target_bpp,
-                               &stream->sink->sink_dsc_caps.dsc_dec_caps,
+                               &stream->sink->dsc_caps.dsc_dec_caps,
                                &stream->timing, &params[count].bw_range))
                        params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 
@@ -857,7 +857,7 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
                if (!aconnector || !aconnector->dc_sink)
                        continue;
 
-               if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+               if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
                        continue;
 
                if (computed_streams[i])

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 83df17a17271d88d3911785c88b5cd781fab4565..fb603bd46fac9554d9df4f502da4a1bf1f04edc7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3407,7 +3407,7 @@ uint32_t dc_link_bandwidth_kbps(
        link_bw_kbps *= 8;   /* 8 bits per byte*/
        link_bw_kbps *= link_setting->lane_count;
 
-       if (dc_link_is_fec_supported(link)) {
+       if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
                /* Account for FEC overhead.
                 * We have to do it based on caps,
                 * and not based on FEC being set ready,
@@ -3456,7 +3456,6 @@ bool dc_link_is_fec_supported(const struct dc_link *link)
        return (dc_is_dp_signal(link->connector_signal) &&
                        link->link_enc->features.fec_supported &&
                        link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
-                       !link->dc->debug.disable_fec &&
                        !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index fc3664dd5e885814d088db2ab25cba8a1e4b4461..9553755be286d11667aa35e3c8ea3e12f9321faa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4152,7 +4152,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
        struct link_encoder *link_enc = link->link_enc;
        uint8_t fec_config = 0;
 
-       if (!dc_link_is_fec_supported(link))
+       if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
                return;
 
        if (link_enc->funcs->fec_set_ready &&
@@ -4187,7 +4187,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
 {
        struct link_encoder *link_enc = link->link_enc;
 
-       if (!dc_link_is_fec_supported(link))
+       if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
                return;
 
        if (link_enc->funcs->fec_set_enable &&

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 2b538f477c82c6ca1f5f182d597fba46a49b4cee..5508c32f4484c81853c8a1b15826fa07ecdba132 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1025,6 +1025,11 @@ struct dc_sink_dsc_caps {
        struct dsc_dec_dpcd_caps dsc_dec_caps;
 };
 
+struct dc_sink_fec_caps {
+       bool is_rx_fec_supported;
+       bool is_topology_fec_supported;
+};
+
 /*
  * The sink structure contains EDID and other display device properties
  */
@@ -1038,7 +1043,8 @@ struct dc_sink {
        struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
        bool converter_disable_audio;
 
-       struct dc_sink_dsc_caps sink_dsc_caps;
+       struct dc_sink_dsc_caps dsc_caps;
+       struct dc_sink_fec_caps fec_caps;
 
        /* private to DC core */
        struct dc_link *link;