tools/power turbostat: further decode MSR_IA32_MISC_ENABLE

Decode MISC_ENABLE.NO_TURBO,
also use the #defines in msr-index.h for decoding this register

cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)

Although it is not architectural, decode also
MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9).
documented to be present on: Core, P4, Intel-Xeon
reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec.

Signed-off-by: Len Brown <len.brown@intel.com>

diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 762b81497c3bf52e45daf1d90240bb424c096bc4..a1ec9d816dfa94e9d753ca793121dd112f38b237 100644 (file)
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -3509,11 +3509,13 @@ void decode_misc_enable_msr(void)
        unsigned long long msr;
 
        if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
-               fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",
+               fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
                        base_cpu, msr,
-                       msr & (1 << 3) ? "TCC" : "",
-                       msr & (1 << 16) ? "EIST" : "",
-                       msr & (1 << 18) ? "MONITOR" : "");
+                       msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
+                       msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
+                       msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "",
+                       msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
+                       msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
 }
 
 /*