riscv: Move global pointer loading to a macro

In Clang 17, -fsanitize=shadow-call-stack uses the newly declared
platform register gp for storing shadow call stack pointers. As
this is obviously incompatible with gp relaxation, in preparation
for CONFIG_SHADOW_CALL_STACK support, move global pointer loading
to a single macro, which we can cleanly disable when SCS is used
instead.

Link: https://reviews.llvm.org/rGaa1d2693c256
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444d769
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20230927224757.1154247-11-samitolvanen@google.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
index 8e446be2d57cfdaea800a55e8fcc80a8ce6b4078..f34dd1a526a125f8a357bb860d0c474ff04b9415 100644 (file)
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -109,6 +109,14 @@
        REG_L \dst, 0(\dst)
 .endm
 
+/* load __global_pointer to gp */
+.macro load_global_pointer
+.option push
+.option norelax
+       la gp, __global_pointer$
+.option pop
+.endm
+
        /* save all GPs except x1 ~ x5 */
        .macro save_from_x6_to_x31
        REG_S x6,  PT_T1(sp)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index a306562636e4920c55335e360018b5120817d199..6215dcf2e83becb46eeb39301c15495e6e20ef3d 100644 (file)
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -75,10 +75,8 @@ _save_context:
        csrw CSR_SCRATCH, x0
 
        /* Load the global pointer */
-.option push
-.option norelax
-       la gp, __global_pointer$
-.option pop
+       load_global_pointer
+
        move a0, sp /* pt_regs */
        la ra, ret_from_exception
 

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 3710ea5d160f30347ff1b8ebf79927ca466e6da1..a0484d95d8fb3dd859b5de48421fe9315cca26ea 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -110,10 +110,7 @@ relocate_enable_mmu:
        csrw CSR_TVEC, a0
 
        /* Reload the global pointer */
-.option push
-.option norelax
-       la gp, __global_pointer$
-.option pop
+       load_global_pointer
 
        /*
         * Switch to kernel page tables.  A full fence is necessary in order to
@@ -134,10 +131,7 @@ secondary_start_sbi:
        csrw CSR_IP, zero
 
        /* Load the global pointer */
-       .option push
-       .option norelax
-               la gp, __global_pointer$
-       .option pop
+       load_global_pointer
 
        /*
         * Disable FPU & VECTOR to detect illegal usage of
@@ -228,10 +222,7 @@ pmp_done:
 #endif /* CONFIG_RISCV_M_MODE */
 
        /* Load the global pointer */
-.option push
-.option norelax
-       la gp, __global_pointer$
-.option pop
+       load_global_pointer
 
        /*
         * Disable FPU & VECTOR to detect illegal usage of

diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S
index f7960c7c5f9e25081424f3edbe526896c1692303..d5cf8b57577739f5ae615b1e3cbd1b117dbeff19 100644 (file)
--- a/arch/riscv/kernel/suspend_entry.S
+++ b/arch/riscv/kernel/suspend_entry.S
@@ -61,10 +61,7 @@ END(__cpu_suspend_enter)
 
 SYM_TYPED_FUNC_START(__cpu_resume_enter)
        /* Load the global pointer */
-       .option push
-       .option norelax
-               la gp, __global_pointer$
-       .option pop
+       load_global_pointer
 
 #ifdef CONFIG_MMU
        /* Save A0 and A1 */