drm/amd/powerplay: revise calling chain on retrieving frequency range

This helps to maintain clear code layers and drop unnecessary
parameter.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index fb89204c0070f7882594aae425de7ec101bdea1b..e16e58ede1ca51ccdea3a7d391700577ddd9e254 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1461,7 +1461,7 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val)
        }
 
        if (is_support_sw_smu(adev)) {
-               ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq, true);
+               ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq);
                if (ret || val > max_freq || val < min_freq)
                        return -EINVAL;
                ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 6a39996487b9c514871c93bd7f6f6152eeba42d2..64b42324d104ac7cd76a51a95caa87dc4153b1c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -911,8 +911,7 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
        if (is_support_sw_smu(adev)) {
                ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
                                             low ? &clk_freq : NULL,
-                                            !low ? &clk_freq : NULL,
-                                            true);
+                                            !low ? &clk_freq : NULL);
                if (ret)
                        return 0;
                return clk_freq * 100;
@@ -929,8 +928,7 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
        if (is_support_sw_smu(adev)) {
                ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
                                             low ? &clk_freq : NULL,
-                                            !low ? &clk_freq : NULL,
-                                            true);
+                                            !low ? &clk_freq : NULL);
                if (ret)
                        return 0;
                return clk_freq * 100;

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 560df8593d3264b429d096b594d363248aa99e0c..95685bb9582adc358da28c7720f88038a794b58f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -261,51 +261,25 @@ int smu_set_soft_freq_range(struct smu_context *smu,
        return ret;
 }
 
-int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
-                          uint32_t *min, uint32_t *max, bool lock_needed)
+int smu_get_dpm_freq_range(struct smu_context *smu,
+                          enum smu_clk_type clk_type,
+                          uint32_t *min,
+                          uint32_t *max)
 {
-       uint32_t clock_limit;
        int ret = 0;
 
        if (!min && !max)
                return -EINVAL;
 
-       if (lock_needed)
-               mutex_lock(&smu->mutex);
-
-       if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
-               switch (clk_type) {
-               case SMU_MCLK:
-               case SMU_UCLK:
-                       clock_limit = smu->smu_table.boot_values.uclk;
-                       break;
-               case SMU_GFXCLK:
-               case SMU_SCLK:
-                       clock_limit = smu->smu_table.boot_values.gfxclk;
-                       break;
-               case SMU_SOCCLK:
-                       clock_limit = smu->smu_table.boot_values.socclk;
-                       break;
-               default:
-                       clock_limit = 0;
-                       break;
-               }
+       mutex_lock(&smu->mutex);
 
-               /* clock in Mhz unit */
-               if (min)
-                       *min = clock_limit / 100;
-               if (max)
-                       *max = clock_limit / 100;
-       } else {
-               /*
-                * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
-                * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
-                */
-               ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
-       }
+       if (smu->ppt_funcs->get_dpm_ultimate_freq)
+               ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
+                                                           clk_type,
+                                                           min,
+                                                           max);
 
-       if (lock_needed)
-               mutex_unlock(&smu->mutex);
+       mutex_unlock(&smu->mutex);
 
        return ret;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ceabce4b4a5f579b2033b7245f067523cfef54df..ae16cc4c2b2d1aa5db7ee6abcfd9c5306babdeec 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -720,7 +720,7 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t *value);
 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
-                          uint32_t *min, uint32_t *max, bool lock_needed);
+                          uint32_t *min, uint32_t *max);
 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t min, uint32_t max);
 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 1da4f6fc3e7ac1e9ffb08b4e1edb1ec973a9c582..d88b2f200d94335e9369262208188d30d78cb2ca 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1082,13 +1082,13 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
        int ret = 0;
        uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 
-       ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
+       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_SCLK, &min_sclk_freq, NULL);
        if (ret)
                return ret;
 
        smu->pstate_sclk = min_sclk_freq * 100;
 
-       ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
+       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_MCLK, &min_mclk_freq, NULL);
        if (ret)
                return ret;
 
@@ -1143,7 +1143,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
                return ret;
 
        if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
-               ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
+               ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
                if (ret)
                        return ret;
                ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
@@ -1185,7 +1185,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 
        for (i = 0; i < ARRAY_SIZE(clks); i++) {
                clk_type = clks[i];
-               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+               ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
 
@@ -1212,7 +1212,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
 
        for (i = 0; i < ARRAY_SIZE(clks); i++) {
                clk_type = clks[i];
-               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+               ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
 

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 0da8dc3fb7b9ea4c1cc9665b7b6c60c7977cbc6f..d4aa01a05c54181b538ed669630d690c31a1553f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -264,7 +264,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
        case SMU_SCLK:
                /* retirve table returned paramters unit is MHz */
                cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
-               ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
+               ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
                if (!ret) {
                        /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
                        if (cur_value  == max)
@@ -434,7 +434,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
 
        for (i = 0; i < ARRAY_SIZE(clks); i++) {
                clk_type = clks[i];
-               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+               ret = smu_v12_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
 
@@ -468,7 +468,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
 
                clk_type = clk_feature_map[i].clk_type;
 
-               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+               ret = smu_v12_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
 
@@ -633,7 +633,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
                        return -EINVAL;
                }
 
-               ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
+               ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
                if (ret)
                        return ret;
                ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
@@ -716,7 +716,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
        int ret = 0;
        uint32_t sclk_freq = 0, uclk_freq = 0;
 
-       ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
+       ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
        if (ret)
                return ret;
 
@@ -724,7 +724,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
        if (ret)
                return ret;
 
-       ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
+       ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
        if (ret)
                return ret;
 

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 1e8b4c50d518986842af46407bac84372b698cde..11df0a91dd3cb2c835eeacb1df9440673f4a99f6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -929,13 +929,13 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
        int ret = 0;
        uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 
-       ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
+       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_SCLK, &min_sclk_freq, NULL);
        if (ret)
                return ret;
 
        smu->pstate_sclk = min_sclk_freq * 100;
 
-       ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
+       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_MCLK, &min_mclk_freq, NULL);
        if (ret)
                return ret;
 
@@ -958,7 +958,7 @@ static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
 #endif
 
        if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
-               ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
+               ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
                if (ret)
                        return ret;
                ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
@@ -1002,7 +1002,7 @@ static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool hi
 
        for (i = 0; i < ARRAY_SIZE(clks); i++) {
                clk_type = clks[i];
-               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+               ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
 
@@ -1029,7 +1029,7 @@ static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
 
        for (i = 0; i < ARRAY_SIZE(clks); i++) {
                clk_type = clks[i];
-               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+               ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
 

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 2d89b195adbe3a26fe9cdba2ad3ac5b8d732e8ea..c4d1e7020e1fb4b590daaf291e0a1371fbcab16a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1699,6 +1699,34 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
 {
        int ret = 0, clk_id = 0;
        uint32_t param = 0;
+       uint32_t clock_limit;
+
+       if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
+               switch (clk_type) {
+               case SMU_MCLK:
+               case SMU_UCLK:
+                       clock_limit = smu->smu_table.boot_values.uclk;
+                       break;
+               case SMU_GFXCLK:
+               case SMU_SCLK:
+                       clock_limit = smu->smu_table.boot_values.gfxclk;
+                       break;
+               case SMU_SOCCLK:
+                       clock_limit = smu->smu_table.boot_values.socclk;
+                       break;
+               default:
+                       clock_limit = 0;
+                       break;
+               }
+
+               /* clock in Mhz unit */
+               if (min)
+                       *min = clock_limit / 100;
+               if (max)
+                       *max = clock_limit / 100;
+
+               return 0;
+       }
 
        clk_id = smu_clk_get_index(smu, clk_type);
        if (clk_id < 0) {

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index e46fc61782359c975de85cc1fdbe9cf2165cec2e..6400a0acad6314bcdf17affecac63aad09a55b1b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -321,6 +321,34 @@ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
 {
        int ret = 0;
        uint32_t mclk_mask, soc_mask;
+       uint32_t clock_limit;
+
+       if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
+               switch (clk_type) {
+               case SMU_MCLK:
+               case SMU_UCLK:
+                       clock_limit = smu->smu_table.boot_values.uclk;
+                       break;
+               case SMU_GFXCLK:
+               case SMU_SCLK:
+                       clock_limit = smu->smu_table.boot_values.gfxclk;
+                       break;
+               case SMU_SOCCLK:
+                       clock_limit = smu->smu_table.boot_values.socclk;
+                       break;
+               default:
+                       clock_limit = 0;
+                       break;
+               }
+
+               /* clock in Mhz unit */
+               if (min)
+                       *min = clock_limit / 100;
+               if (max)
+                       *max = clock_limit / 100;
+
+               return 0;
+       }
 
        if (max) {
                ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,