mmc: mtk-sd: Assign src_clk parent to src_clk_cg for legacy DTs

In commit 3c1a88443698 ("mmc: mediatek: add support of source_cg clock")
an independent cg was introduced to avoid a hardware hang issue during
clock mode switches (subsequent commits will set that clock as optional).

When this clock is not present in device-tree, any operation is being
done on src_clk's parent (calling clk_get_parent()): to simplify this
and avoid checking for src_clk_cg presence everytime, just assign the
parent clock to src_clk_cg and remove the now useless checks.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20211216125748.179602-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 59d7decc305128d0d5792845a12d332f0bfe3ee0..65037e1d7723b8ad23a80489bdf21bf172654689 100644 (file)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -901,14 +901,8 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
                }
        }
        sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
-       /*
-        * As src_clk/HCLK use the same bit to gate/ungate,
-        * So if want to only gate src_clk, need gate its parent(mux).
-        */
-       if (host->src_clk_cg)
-               clk_disable_unprepare(host->src_clk_cg);
-       else
-               clk_disable_unprepare(clk_get_parent(host->src_clk));
+
+       clk_disable_unprepare(host->src_clk_cg);
        if (host->dev_comp->clk_div_bits == 8)
                sdr_set_field(host->base + MSDC_CFG,
                              MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
@@ -917,11 +911,8 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
                sdr_set_field(host->base + MSDC_CFG,
                              MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
                              (mode << 12) | div);
-       if (host->src_clk_cg)
-               clk_prepare_enable(host->src_clk_cg);
-       else
-               clk_prepare_enable(clk_get_parent(host->src_clk));
 
+       clk_prepare_enable(host->src_clk_cg);
        readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
        sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
        mmc->actual_clock = sclk;
@@ -2530,6 +2521,19 @@ static int msdc_of_clock_parse(struct platform_device *pdev,
        if (IS_ERR(host->src_clk_cg))
                return PTR_ERR(host->src_clk_cg);
 
+       /*
+        * Fallback for legacy device-trees: src_clk and HCLK use the same
+        * bit to control gating but they are parented to a different mux,
+        * hence if our intention is to gate only the source, required
+        * during a clk mode switch to avoid hw hangs, we need to gate
+        * its parent (specified as a different clock only on new DTs).
+        */
+       if (!host->src_clk_cg) {
+               host->src_clk_cg = clk_get_parent(host->src_clk);
+               if (IS_ERR(host->src_clk_cg))
+                       return PTR_ERR(host->src_clk_cg);
+       }
+
        host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg");
        if (IS_ERR(host->sys_clk_cg))
                host->sys_clk_cg = NULL;