#include "ebony.h"
#include <asm/processor.h>
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
-long int fixed_sdram( void );
+long int fixed_sdram (void);
int board_pre_init (void)
{
uint reg;
+ unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+ unsigned char status;
+
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
- mtdcr( ebccfga, xbcfg );
- reg = mfdcr( ebccfgd );
- mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
-
- mtebc( pb0ap, 0x9b015480 ); /* FLASH/SRAM */
- mtebc( pb0cr, 0xfff18000 ); /* BAS=0xfff 1MB R/W 8-bit */
- mtebc( pb1ap, 0x02815480 ); /* NVRAM/RTC */
- mtebc( pb1cr, 0x48018000 ); /* BA=0x480 1MB R/W 8-bit */
- mtebc( pb2ap, 0x9b015480 ); /* 4MB FLASH */
- mtebc( pb2cr, 0xff858000 ); /* BAS=0xff8 4MB R/W 8-bit */
- mtebc( pb7ap, 0x01015280 ); /* FPGA registers */
- mtebc( pb7cr, 0x48318000 ); /* BA=0x483 1MB R/W 8-bit */
+ mtdcr (ebccfga, xbcfg);
+ reg = mfdcr (ebccfgd);
+ mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */
+
+ mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */
+ mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
+ mtebc (pb7ap, 0x01015280); /* FPGA registers */
+ mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
+
+ /* read FPGA_REG0 and set the bus controller */
+ status = *fpga_base;
+ if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
+ mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */
+ mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
+ mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */
+ mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
+ } else {
+ mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */
+ mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
+
+ /* set CS2 if FLASH_ONBD_N == 0 */
+ if (!(status & FLASH_ONBD_N)) {
+ mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */
+ mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
+ }
+ }
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr( uic0sr, 0xffffffff ); /* clear all */
- mtdcr( uic0er, 0x00000000 ); /* disable all */
- mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
- mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
- mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
- mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
- mtdcr( uic0sr, 0xffffffff ); /* clear all */
-
- mtdcr( uic1sr, 0xffffffff ); /* clear all */
- mtdcr( uic1er, 0x00000000 ); /* disable all */
- mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
- mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
- mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
- mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
- mtdcr( uic1sr, 0xffffffff ); /* clear all */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr (uic1er, 0x00000000); /* disable all */
+ mtdcr (uic1cr, 0x00000000); /* all non-critical */
+ mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
return 0;
}
int checkboard (void)
{
sys_info_t sysinfo;
- get_sys_info(&sysinfo);
-
- printf("IBM 440GP Evaluation Board (Ebony)\n");
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
+
+ get_sys_info (&sysinfo);
+
+ printf ("IBM 440GP Evaluation Board (Ebony)\n");
+ printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
long int initdram (int board_type)
{
- long dram_size = 0;
+ long dram_size = 0;
+
#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram();
+ dram_size = spd_sdram ();
#else
- dram_size = fixed_sdram();
+ dram_size = fixed_sdram ();
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
-int testdram(void)
+int testdram (void)
{
- uint *pstart = (uint *)0x00000000;
- uint *pend = (uint *)0x08000000;
- uint *p;
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) 0x08000000;
+ uint *p;
- for( p = pstart; p < pend; p++ )
+ for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
- for( p = pstart; p < pend; p++ )
- {
- if( *p != 0xaaaaaaaa )
- {
- printf("SDRAM test fails at: %08x\n", (uint)p );
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
- for( p = pstart; p < pend; p++ )
+ for (p = pstart; p < pend; p++)
*p = 0x55555555;
- for( p = pstart; p < pend; p++ )
- {
- if( *p != 0x55555555 )
- {
- printf("SDRAM test fails at: %08x\n", (uint)p );
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
* PLB @ 133 MHz
*
************************************************************************/
-long int fixed_sdram( void )
+long int fixed_sdram (void)
{
- uint reg;
+ uint reg;
+
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
- mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
- mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
- mtsdram( mem_wddctr,0x00000000 ); /* wrcp=0 dcd=0 */
- mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram( mem_b0cr, 0x000a4001 );/* SDBA=0x000 128MB, Mode 3, enabled*/
- mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
- mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
- udelay( 400 ); /* Delay 200 usecs (min) */
-
+ mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay (400); /* Delay 200 usecs (min) */
+
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
- for(;;)
- {
- mfsdram( mem_mcsts, reg );
- if( reg & 0x80000000 )
+ mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram (mem_mcsts, reg);
+ if (reg & 0x80000000)
break;
}
-
- return( 128 * 1024 * 1024 ); /* 128 MB */
+
+ return (128 * 1024 * 1024); /* 128 MB */
}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
+#endif /* !defined(CONFIG_SPD_EEPROM) */
tx_i_index = 0; /* Transmit Interrupt Queue Index */
tx_u_index = 0; /* Transmit User Queue Index */
+#if defined(CONFIG_440)
+ /* set RMII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+#endif /* CONFIG_440 */
+
/* EMAC RESET */
out32 (EMAC_M0, EMAC_M0_SRST);
/* set transmit request threshold register */
out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
- /* set recieve low/high water mark register */
+ /* set receive low/high water mark register */
+#if defined(CONFIG_440)
+ /* 440GP has a 64 byte burst length */
+ out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
+ out32 (EMAC_TXM1, 0xf8640000);
+#else /* CONFIG_440 */
+ /* 405s have a 16 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
+#endif /* CONFIG_440 */
/* Frame gap set */
out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
tx[tx_slot].data_len = (short) len;
tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
+ __asm__ volatile ("eieio");
out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
#ifdef INFO_405_ENET
packetSent++;
}
+#if defined(CONFIG_440)
+/*-----------------------------------------------------------------------------+
+| EnetInt.
+| EnetInt is the interrupt handler. It will determine the
+| cause of the interrupt and call the apporpriate servive
+| routine.
++-----------------------------------------------------------------------------*/
+int enetInt ()
+{
+ int serviced;
+ int rc = -1; /* default to not us */
+ unsigned long mal_isr;
+ unsigned long emac_isr = 0;
+ unsigned long mal_rx_eob;
+ unsigned long my_uic0msr, my_uic1msr;
+
+ /* enter loop that stays in interrupt code until nothing to service */
+ do {
+ serviced = 0;
+
+ my_uic0msr = mfdcr (uic0msr);
+ my_uic1msr = mfdcr (uic1msr);
+
+ if (!(my_uic0msr & UIC_MRE)
+ && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ /* not for us */
+ return (rc);
+ }
+
+ /* get and clear controller status interrupts */
+ /* look at Mal and EMAC interrupts */
+ if ((my_uic0msr & UIC_MRE)
+ || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ /* we have a MAL interrupt */
+ mal_isr = mfdcr (malesr);
+ /* look for mal error */
+ if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
+ mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
+ emac_isr = in32 (EMAC_ISR);
+ if ((emac_ier & emac_isr) != 0) {
+ emac_err (emac_isr);
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ if ((emac_ier & emac_isr)
+ || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ mtdcr (uic0sr, UIC_MRE); /* Clear */
+ mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ return (rc); /* we had errors so get out */
+ }
+
+ /* handle MAL RX EOB interupt from a receive */
+ /* check for EOB on valid channels */
+ if (my_uic0msr & UIC_MRE) {
+ mal_rx_eob = mfdcr (malrxeobisr);
+ if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
+ /* clear EOB
+ mtdcr(malrxeobisr, mal_rx_eob); */
+ enet_rcv (emac_isr);
+ /* indicate that we serviced an interrupt */
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ mtdcr (uic0sr, UIC_MRE); /* Clear */
+ mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ } while (serviced);
+
+ return (rc);
+}
+#else /* CONFIG_440 */
/*-----------------------------------------------------------------------------+
* EnetInt.
* EnetInt is the interrupt handler. It will determine the
return (rc);
}
+#endif /* CONFIG_440 */
/*-----------------------------------------------------------------------------+
* MAL Error Routine
mtdcr (maltxdeir, 0xC0000000);
mtdcr (malrxdeir, 0x80000000);
-#if 0 /*sr */
+#if 1 /*sr */
printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
isr, uic, maldef, mal_errr);
#else
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