drm/i915: introduce crtc->dspaddr_offset

To avoid recomputing the display framebuffer offset on gen2/3
pageflips. This is also prep work to do similar trickery on gen4+

Also:
- kill "Start", such upper-case remnants from the ddx must surely die.
- rename "Offset" to linear_offset, to make it clearer that on gen4+
  this is only used by the hw for linear buffers, for tiled buffers it
  uses the TILEOFF register.
- call DSAPADDR DSPLINOFF on gen4+ for the same reason (and because
  the documentation really renamed the register).

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1bd17e7dd479d0d848e0f52c70164adafdda343d..4a2ea42b5ecf6037fee37152fedd7c1d22040ea0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2979,6 +2979,7 @@
 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
+#define DSPLINOFF(plane) DSPADDR(plane)
 
 /* Display/Sprite base address macros */
 #define DISP_BASEADDR_MASK     (0xfffff000)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7e31f7af0de8761bf3228f8281f92dced0af7f07..f8c24123dde0b33d877909f7e618feef7b6de67a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1982,7 +1982,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int plane = intel_crtc->plane;
-       unsigned long Start, Offset;
+       unsigned long linear_offset;
        u32 dspcntr;
        u32 reg;
 
@@ -2029,18 +2029,22 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 
        I915_WRITE(reg, dspcntr);
 
-       Start = obj->gtt_offset;
-       Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+       linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 
-       DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-                     Start, Offset, x, y, fb->pitches[0]);
+       if (INTEL_INFO(dev)->gen >= 4)
+               intel_crtc->dspaddr_offset = 0;
+       else
+               intel_crtc->dspaddr_offset = linear_offset;
+
+       DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
+                     obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
        if (INTEL_INFO(dev)->gen >= 4) {
-               I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
+               I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset);
                I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
-               I915_WRITE(DSPADDR(plane), Offset);
+               I915_WRITE(DSPLINOFF(plane), linear_offset);
        } else
-               I915_WRITE(DSPADDR(plane), Start + Offset);
+               I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
        POSTING_READ(reg);
 
        return 0;
@@ -2055,7 +2059,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int plane = intel_crtc->plane;
-       unsigned long Start, Offset;
+       unsigned long linear_offset;
        u32 dspcntr;
        u32 reg;
 
@@ -2110,15 +2114,15 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 
        I915_WRITE(reg, dspcntr);
 
-       Start = obj->gtt_offset;
-       Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+       linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+       intel_crtc->dspaddr_offset = 0;
 
-       DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-                     Start, Offset, x, y, fb->pitches[0]);
+       DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
+                     obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
-       I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
+       I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset);
        I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
-       I915_WRITE(DSPADDR(plane), Offset);
+       I915_WRITE(DSPLINOFF(plane), linear_offset);
        POSTING_READ(reg);
 
        return 0;
@@ -6194,7 +6198,6 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       unsigned long offset;
        u32 flip_mask;
        struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
        int ret;
@@ -6203,9 +6206,6 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
        if (ret)
                goto err;
 
-       /* Offset into the new buffer for cases of shared fbs between CRTCs */
-       offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
-
        ret = intel_ring_begin(ring, 6);
        if (ret)
                goto err_unpin;
@@ -6222,7 +6222,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, MI_DISPLAY_FLIP |
                        MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
        intel_ring_emit(ring, fb->pitches[0]);
-       intel_ring_emit(ring, obj->gtt_offset + offset);
+       intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
        intel_ring_emit(ring, 0); /* aux display base address, unused */
        intel_ring_advance(ring);
        return 0;
@@ -6240,7 +6240,6 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       unsigned long offset;
        u32 flip_mask;
        struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
        int ret;
@@ -6249,9 +6248,6 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
        if (ret)
                goto err;
 
-       /* Offset into the new buffer for cases of shared fbs between CRTCs */
-       offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
-
        ret = intel_ring_begin(ring, 6);
        if (ret)
                goto err_unpin;
@@ -6265,7 +6261,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
                        MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
        intel_ring_emit(ring, fb->pitches[0]);
-       intel_ring_emit(ring, obj->gtt_offset + offset);
+       intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
        intel_ring_emit(ring, MI_NOOP);
 
        intel_ring_advance(ring);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bc6d6165e37eecc4f6f74275d4875f3c2e5e89eb..b7859e7110a7526a1ed897958be8f99a91798677 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -177,6 +177,11 @@ struct intel_crtc {
        struct intel_unpin_work *unpin_work;
        int fdi_lanes;
 
+       /* Display surface base address adjustement for pageflips. Note that on
+        * gen4+ this only adjusts up to a tile, offsets within a tile are
+        * handled in the hw itself (with the TILEOFF register). */
+       unsigned long dspaddr_offset;
+
        struct drm_i915_gem_object *cursor_bo;
        uint32_t cursor_addr;
        int16_t cursor_x, cursor_y;