Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64...

Pull second set of arm64 updates from Catalin Marinas:
 "A second pull request for this merging window, mainly with fixes and
  docs clarification:

   - Documentation clarification on CPU topology and booting
     requirements
   - Additional cache flushing during boot (needed in the presence of
     external caches or under virtualisation)
   - DMA range invalidation fix for non cache line aligned buffers
   - Build failure fix with !COMPAT
   - Kconfig update for STRICT_DEVMEM"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Fix DMA range invalidation for cache line unaligned buffers
  arm64: Add missing Kconfig for CONFIG_STRICT_DEVMEM
  arm64: fix !CONFIG_COMPAT build failures
  Revert "arm64: virt: ensure visibility of __boot_cpu_mode"
  arm64: Relax the kernel cache requirements for boot
  arm64: Update the TCR_EL1 translation granule definitions for 16K pages
  ARM: topology: Make it clear that all CPUs need to be described

diff --cc arch/arm64/kernel/head.S
index 1fe5d8d2bdfd2f8c134cde57e968d026db854f0f,26109682d2fad765c50fcf56b12a2c0b7ef8c6eb..0fd56500077271402bb7af82f83526cd1dcef1ee
--- 1/arch/arm64/kernel/head.S
--- 2/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@@ -461,12 -476,26 +476,23 @@@ __create_page_tables
        sub     x6, x6, #1                      // inclusive range
        create_block_map x0, x7, x3, x5, x6
  1:
 -#ifdef CONFIG_EARLY_PRINTK
        /*
 -       * Create the pgd entry for the UART mapping. The full mapping is done
 -       * later based earlyprintk kernel parameter.
 +       * Create the pgd entry for the fixed mappings.
         */
 -      ldr     x5, =EARLYCON_IOBASE            // UART virtual address
 +      ldr     x5, =FIXADDR_TOP                // Fixed mapping virtual address
        add     x0, x26, #2 * PAGE_SIZE         // section table address
        create_pgd_entry x26, x0, x5, x6, x7
 -#endif
+ 
+       /*
+        * Since the page tables have been populated with non-cacheable
+        * accesses (MMU disabled), invalidate the idmap and swapper page
+        * tables again to remove any speculatively loaded cache lines.
+        */
+       mov     x0, x25
+       add     x1, x26, #SWAPPER_DIR_SIZE
+       bl      __inval_cache_range
+ 
+       mov     lr, x27
        ret
  ENDPROC(__create_page_tables)
        .ltorg