]> www.infradead.org Git - users/willy/xarray.git/commitdiff
arm64: dts: ti: k3-am64: Reserve timers used by MCU FW
authorHari Nagalla <hnagalla@ti.com>
Fri, 2 May 2025 22:03:25 +0000 (17:03 -0500)
committerNishanth Menon <nm@ti.com>
Tue, 6 May 2025 12:29:51 +0000 (07:29 -0500)
AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses
main domain timers as tick timers in these firmwares. Hence keep them
as reserved in the Linux device tree.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20250502220325.3230653-12-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-am642-evm.dts
arch/arm64/boot/dts/ti/k3-am642-sk.dts

index 5c6197ba842e4e1c604d3063d25b7f99c274057f..e01866372293babcbe6687f32a094e9daaa815ec 100644 (file)
        status = "okay";
 };
 
+/* main_timer8 is used by r5f0-0 */
+&main_timer8 {
+       status = "reserved";
+};
+
+/* main_timer9 is used by r5f0-1 */
+&main_timer9 {
+       status = "reserved";
+};
+
+/* main_timer10 is used by r5f1-0 */
+&main_timer10 {
+       status = "reserved";
+};
+
+/* main_timer11 is used by r5f1-1 */
+&main_timer11 {
+       status = "reserved";
+};
+
 &serdes_ln_ctrl {
        idle-states = <AM64_SERDES0_LANE0_PCIE0>;
 };
index 33e421ec18abbc5d3f6090494d4f823bbd63f35c..1deaa0be0085c4e64136d3e8f68fdcd62ca7e068 100644 (file)
        status = "okay";
 };
 
+/* main_timer8 is used by r5f0-0 */
+&main_timer8 {
+       status = "reserved";
+};
+
+/* main_timer9 is used by r5f0-1 */
+&main_timer9 {
+       status = "reserved";
+};
+
+/* main_timer10 is used by r5f1-0 */
+&main_timer10 {
+       status = "reserved";
+};
+
+/* main_timer11 is used by r5f1-1 */
+&main_timer11 {
+       status = "reserved";
+};
+
 &ecap0 {
        status = "okay";
        /* PWM is available on Pin 1 of header J3 */