drm/i915/gt: Correct prefix on a few registers

We have a few registers that have existed for several hardware
generations, but are only used by the driver on Xe_HP and beyond.  In
cases where the Xe_HP version of the register is now replicated and uses
multicast behavior, but earlier generations were singleton, let's change
the register prefix to "XEHP_" to help clarify that we're using the
newer multicast form of the register.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-5-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index be6f0066c2a801d2d72fcf11a3c394a54b3c73dd..cf965ade8d908f03e756c43f8ee87ac25b4abf52 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -483,7 +483,7 @@
 
 #define GEN8_RC6_CTX_INFO                      _MMIO(0x8504)
 
-#define GEN12_SQCM                             _MMIO(0x8724)
+#define XEHP_SQCM                              _MMIO(0x8724)
 #define   EN_32B_ACCESS                                REG_BIT(30)
 
 #define HSW_IDICR                              _MMIO(0x9008)
@@ -986,7 +986,7 @@
 #define GEN11_SCRATCH2                         _MMIO(0xb140)
 #define   GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE    (1 << 19)
 
-#define GEN11_L3SQCREG5                                _MMIO(0xb158)
+#define XEHP_L3SQCREG5                         _MMIO(0xb158)
 #define   L3_PWM_TIMER_INIT_VAL_MASK           REG_GENMASK(9, 0)
 
 #define MLTICTXCTL                             _MMIO(0xb170)
@@ -1050,7 +1050,7 @@
 #define GEN12_COMPCTX_TLB_INV_CR               _MMIO(0xcf04)
 #define XEHP_COMPCTX_TLB_INV_CR                        _MMIO(0xcf04)
 
-#define GEN12_MERT_MOD_CTRL                    _MMIO(0xcf28)
+#define XEHP_MERT_MOD_CTRL                     _MMIO(0xcf28)
 #define RENDER_MOD_CTRL                                _MMIO(0xcf2c)
 #define COMP_MOD_CTRL                          _MMIO(0xcf30)
 #define VDBX_MOD_CTRL                          _MMIO(0xcf34)
@@ -1152,7 +1152,7 @@
 #define EU_PERF_CNTL1                          _MMIO(0xe558)
 #define EU_PERF_CNTL5                          _MMIO(0xe55c)
 
-#define GEN12_HDC_CHICKEN0                     _MMIO(0xe5f0)
+#define XEHP_HDC_CHICKEN0                      _MMIO(0xe5f0)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK       REG_GENMASK(13, 11)
 #define ICL_HDC_MODE                           _MMIO(0xe5f4)
 

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3056b099dd17aa891bd59dafc5a3aee34a8a2058..96b9f02a22845ac44e703613c2c34bb361c7bb7a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,7 +569,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
                                   struct i915_wa_list *wal)
 {
        wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
-       wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+       wa_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
                         REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
        wa_add(wal,
               XEHP_FF_MODE2,
@@ -1514,7 +1514,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
         * recommended tuning settings documented in the bspec's
         * performance guide section.
         */
-       wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
+       wa_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
 
        /* Wa_14015795083 */
        wa_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -2170,7 +2170,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                 * Wa_22010960976:dg2
                 * Wa_14013347512:dg2
                 */
-               wa_masked_dis(wal, GEN12_HDC_CHICKEN0,
+               wa_masked_dis(wal, XEHP_HDC_CHICKEN0,
                              LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
        }
 
@@ -2223,7 +2223,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
            IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
                /* Wa_14012362059:dg2 */
-               wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+               wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
        }
 
        if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
@@ -2816,7 +2816,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                }
 
                /* Wa_14012362059:xehpsdv */
-               wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+               wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
 
                /* Wa_14014368820:xehpsdv */
                wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |