irqchip/imx-mu-msi: Fix wrong register offset for 8ulp

Offset 0x124 should be for IMX_MU_TSR, not IMX_MU_GSR.

Fixes: 70afdab904d2 ("irqchip: Add IMX MU MSI controller driver")
Reported-by: Colin King <colin.i.king@gmail.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[maz: updated commit message, tags]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221004202414.216577-1-Frank.Li@nxp.com

diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c
index b62139dc36e821463aa337653c869c0dbb9eb201..229039eda1b1ff089204fc33764d84de317abdbc 100644 (file)
--- a/drivers/irqchip/irq-imx-mu-msi.c
+++ b/drivers/irqchip/irq-imx-mu-msi.c
@@ -292,7 +292,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
        .xSR    = {
                        [IMX_MU_SR]  = 0xC,
                        [IMX_MU_GSR] = 0x118,
-                       [IMX_MU_GSR] = 0x124,
+                       [IMX_MU_TSR] = 0x124,
                        [IMX_MU_RSR] = 0x12C,
                  },
        .xCR    = {