net: lan743x: Add set RFE read fifo threshold for PCI1x1x chips

PCI11x1x Rev B0 devices might drop packets when receiving back to back frames
at 2.5G link speed. Change the B0 Rev device's Receive filtering Engine FIFO
threshold parameter from its hardware default of 4 to 3 dwords to prevent the
problem. Rev C0 and later hardware already defaults to 3 dwords.

Fixes: bb4f6bffe33c ("net: lan743x: Add PCI11010 / PCI11414 device IDs")
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microchip.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/20240326065805.686128-1-Raju.Lakkaraju@microchip.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c
index bd8aa83b47e5eef1bd523440d2b1a76fedb06d67..75a988c0bd794a83bd31d04b7072e841884ee986 100644 (file)
--- a/drivers/net/ethernet/microchip/lan743x_main.c
+++ b/drivers/net/ethernet/microchip/lan743x_main.c
@@ -25,6 +25,8 @@
 #define PCS_POWER_STATE_DOWN   0x6
 #define PCS_POWER_STATE_UP     0x4
 
+#define RFE_RD_FIFO_TH_3_DWORDS        0x3
+
 static void pci11x1x_strap_get_status(struct lan743x_adapter *adapter)
 {
        u32 chip_rev;
@@ -3272,6 +3274,21 @@ static void lan743x_full_cleanup(struct lan743x_adapter *adapter)
        lan743x_pci_cleanup(adapter);
 }
 
+static void pci11x1x_set_rfe_rd_fifo_threshold(struct lan743x_adapter *adapter)
+{
+       u16 rev = adapter->csr.id_rev & ID_REV_CHIP_REV_MASK_;
+
+       if (rev == ID_REV_CHIP_REV_PCI11X1X_B0_) {
+               u32 misc_ctl;
+
+               misc_ctl = lan743x_csr_read(adapter, MISC_CTL_0);
+               misc_ctl &= ~MISC_CTL_0_RFE_READ_FIFO_MASK_;
+               misc_ctl |= FIELD_PREP(MISC_CTL_0_RFE_READ_FIFO_MASK_,
+                                      RFE_RD_FIFO_TH_3_DWORDS);
+               lan743x_csr_write(adapter, MISC_CTL_0, misc_ctl);
+       }
+}
+
 static int lan743x_hardware_init(struct lan743x_adapter *adapter,
                                 struct pci_dev *pdev)
 {
@@ -3287,6 +3304,7 @@ static int lan743x_hardware_init(struct lan743x_adapter *adapter,
                pci11x1x_strap_get_status(adapter);
                spin_lock_init(&adapter->eth_syslock_spinlock);
                mutex_init(&adapter->sgmii_rw_lock);
+               pci11x1x_set_rfe_rd_fifo_threshold(adapter);
        } else {
                adapter->max_tx_channels = LAN743X_MAX_TX_CHANNELS;
                adapter->used_tx_channels = LAN743X_USED_TX_CHANNELS;

diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h
index be79cb0ae5af339535704547f15e5d8bc3529551..645bc048e52ef50153a1ece92740827d84f4a3f7 100644 (file)
--- a/drivers/net/ethernet/microchip/lan743x_main.h
+++ b/drivers/net/ethernet/microchip/lan743x_main.h
@@ -26,6 +26,7 @@
 #define ID_REV_CHIP_REV_MASK_          (0x0000FFFF)
 #define ID_REV_CHIP_REV_A0_            (0x00000000)
 #define ID_REV_CHIP_REV_B0_            (0x00000010)
+#define ID_REV_CHIP_REV_PCI11X1X_B0_   (0x000000B0)
 
 #define FPGA_REV                       (0x04)
 #define FPGA_REV_GET_MINOR_(fpga_rev)  (((fpga_rev) >> 8) & 0x000000FF)
@@ -311,6 +312,9 @@
 #define SGMII_CTL_LINK_STATUS_SOURCE_  BIT(8)
 #define SGMII_CTL_SGMII_POWER_DN_      BIT(1)
 
+#define MISC_CTL_0                     (0x920)
+#define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4)
+
 /* Vendor Specific SGMII MMD details */
 #define SR_VSMMD_PCS_ID1               0x0004
 #define SR_VSMMD_PCS_ID2               0x0005