PCI: j721e: Add TI J784S4 PCIe configuration

Add PCIe configuration for J784S4 SoC platform which has 4x lane
support.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-6-s-vadapalli@ti.com
Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 645597856a1d938f509c02ade8bbfb2f3859a63b..85718246016b733ee4c8e52ab6c6be2c6f13e93f 100644 (file)
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
        .max_lanes = 1,
 };
 
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+       .mode = PCI_MODE_RC,
+       .quirk_retrain_flag = true,
+       .byte_access_allowed = false,
+       .linkdown_irq_regfield = LINK_DOWN,
+       .max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+       .mode = PCI_MODE_EP,
+       .linkdown_irq_regfield = LINK_DOWN,
+       .max_lanes = 4,
+};
+
 static const struct of_device_id of_j721e_pcie_match[] = {
        {
                .compatible = "ti,j721e-pcie-host",
@@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
                .compatible = "ti,am64-pcie-ep",
                .data = &am64_pcie_ep_data,
        },
+       {
+               .compatible = "ti,j784s4-pcie-host",
+               .data = &j784s4_pcie_rc_data,
+       },
+       {
+               .compatible = "ti,j784s4-pcie-ep",
+               .data = &j784s4_pcie_ep_data,
+       },
        {},
 };