dma_addr_t key_dma_addr = 0;
        struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
        struct device *dev = drvdata_to_dev(ctx->drvdata);
-       u32 larval_addr = cc_larval_digest_addr(ctx->drvdata, ctx->auth_mode);
+       u32 larval_addr;
        struct cc_crypto_req cc_req = {};
        unsigned int blocksize;
        unsigned int digestsize;
                        /* Load hash initial state */
                        hw_desc_init(&desc[idx]);
                        set_cipher_mode(&desc[idx], hashmode);
+                       larval_addr = cc_larval_digest_addr(ctx->drvdata,
+                                                           ctx->auth_mode);
                        set_din_sram(&desc[idx], larval_addr, digestsize);
                        set_flow_mode(&desc[idx], S_DIN_to_HASH);
                        set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
 
        bool is_hmac = ctx->is_hmac;
        struct cc_crypto_req cc_req = {};
        struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
-       cc_sram_addr_t larval_digest_addr =
-               cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
+       cc_sram_addr_t larval_digest_addr;
        int idx = 0;
        int rc = 0;
        gfp_t flags = cc_gfp_flags(&req->base);
                set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
                             ctx->inter_digestsize, NS_BIT);
        } else {
+               larval_digest_addr = cc_larval_digest_addr(ctx->drvdata,
+                                                          ctx->hash_mode);
                set_din_sram(&desc[idx], larval_digest_addr,
                             ctx->inter_digestsize);
        }