drm/amd/display: Enable new interface design for alternate scrambling

[why & how]
To enable a new interface so alternate scrambling can be done via
security module.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d280f55ebe50b8416588a15df7d80f3f0d557d5d..673f36543f6cfd88363d0fc2eeff18bb0c8f544e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -436,6 +436,7 @@ struct dc_config {
        unsigned int disable_ips_in_vpb;
        bool usb4_bw_alloc_support;
        bool allow_0_dtb_clk;
+       bool use_assr_psp_message;
 };
 
 enum visual_confirm {

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index a72de44a5747a446e655536747c40135df2a686a..9c0e2b9cffc9e98ab4971e7e631a54faf489b935 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2285,6 +2285,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
        struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->sink->link;
        struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
+       enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link);
 
        DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
 
@@ -2311,6 +2312,8 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
 
        dc->hwss.disable_audio_stream(pipe_ctx);
 
+       edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false);
+
        update_psp_stream_config(pipe_ctx, true);
        dc->hwss.blank_stream(pipe_ctx);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index e538c67d3ed9152cd773709f7f37bd5c124f2b75..9de5380757e064ca39991a8a206833c136e03843 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -1587,21 +1587,7 @@ bool perform_link_training_with_retries(
                        msleep(delay_dp_power_up_in_ms);
                }
 
-               if (panel_mode == DP_PANEL_MODE_EDP) {
-                       struct cp_psp *cp_psp = &stream->ctx->cp_psp;
-
-                       if (cp_psp && cp_psp->funcs.enable_assr) {
-                               /* ASSR is bound to fail with unsigned PSP
-                                * verstage used during devlopment phase.
-                                * Report and continue with eDP panel mode to
-                                * perform eDP link training with right settings
-                                */
-                               bool result;
-                               result = cp_psp->funcs.enable_assr(cp_psp->handle, link);
-                               if (!result && link->panel_mode != DP_PANEL_MODE_EDP)
-                                       panel_mode = DP_PANEL_MODE_DEFAULT;
-                       }
-               }
+               edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);
 
                dp_set_panel_mode(link, panel_mode);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 3baa2bdd6dd652c919f46529d244ce89b4c9c65c..0682dbbad448dcbfcfb6231d83f9c19228478090 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -38,6 +38,7 @@
 #include "dc/dc_dmub_srv.h"
 #include "dce/dmub_replay.h"
 #include "abm.h"
+#include "resource.h"
 #define DC_LOGGER \
        link->ctx->logger
 #define DC_LOGGER_INIT(logger)
@@ -1145,3 +1146,66 @@ int edp_get_target_backlight_pwm(const struct dc_link *link)
 
        return (int) abm->funcs->get_target_backlight(abm);
 }
+
+static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,
+               struct link_resource *link_res, bool enable)
+{
+       union dmub_rb_cmd cmd;
+       bool use_hpo_dp_link_enc = false;
+       uint8_t link_enc_index = 0;
+       uint8_t phy_type = 0;
+       uint8_t phy_id = 0;
+
+       if (!pDC->config.use_assr_psp_message)
+               return;
+
+       memset(&cmd, 0, sizeof(cmd));
+
+       link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+
+       if (link_res->hpo_dp_link_enc) {
+               link_enc_index = link_res->hpo_dp_link_enc->inst;
+               use_hpo_dp_link_enc = true;
+       }
+
+       if (enable)
+               phy_type = ((dp_get_panel_mode(link) == DP_PANEL_MODE_EDP) ? 1 : 0);
+
+       phy_id = resource_transmitter_to_phy_idx(pDC, link->link_enc->transmitter);
+
+       cmd.assr_enable.header.type = DMUB_CMD__PSP;
+       cmd.assr_enable.header.sub_type = DMUB_CMD__PSP_ASSR_ENABLE;
+       cmd.assr_enable.assr_data.enable = enable;
+       cmd.assr_enable.assr_data.phy_port_type = phy_type;
+       cmd.assr_enable.assr_data.phy_port_id = phy_id;
+       cmd.assr_enable.assr_data.link_enc_index = link_enc_index;
+       cmd.assr_enable.assr_data.hpo_mode = use_hpo_dp_link_enc;
+
+       dc_wake_and_execute_dmub_cmd(pDC->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
+}
+
+void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,
+               enum dp_panel_mode *panel_mode, bool enable)
+{
+       struct link_resource *link_res = &pipe_ctx->link_res;
+       struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
+
+       if (*panel_mode != DP_PANEL_MODE_EDP)
+               return;
+
+       if (link->dc->config.use_assr_psp_message) {
+               edp_set_assr_enable(link->dc, link, link_res, enable);
+       } else if (cp_psp && cp_psp->funcs.enable_assr && enable) {
+               /* ASSR is bound to fail with unsigned PSP
+                * verstage used during devlopment phase.
+                * Report and continue with eDP panel mode to
+                * perform eDP link training with right settings
+                */
+               bool result;
+
+               result = cp_psp->funcs.enable_assr(cp_psp->handle, link);
+
+               if (!result && link->panel_mode != DP_PANEL_MODE_EDP)
+                       *panel_mode = DP_PANEL_MODE_DEFAULT;
+       }
+}

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
index a158c6234d4225e6f665a8082ad351e5ad809d16..eee8a4db6f853ac14c878b5b42cf89d8acb1ca7f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
@@ -76,4 +76,6 @@ bool edp_receiver_ready_T9(struct dc_link *link);
 bool edp_receiver_ready_T7(struct dc_link *link);
 bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable);
 void edp_set_panel_power(struct dc_link *link, bool powerOn);
+void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,
+               enum dp_panel_mode *panel_mode, bool enable);
 #endif /* __DC_LINK_EDP_POWER_CONTROL_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 5b486400dfdb5b725f40952305d4efa964b3ad50..2dfd73d5f767615f8d489f3eace8a902504cff54 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1864,6 +1864,9 @@ static bool dcn351_resource_construct(
        /* Use pipe context based otg sync logic */
        dc->config.use_pipe_ctx_sync_logic = true;
 
+       /* Use psp mailbox to enable assr */
+       dc->config.use_assr_psp_message = true;
+
        /* read VBIOS LTTPR caps */
        {
                if (ctx->dc_bios->funcs->get_lttpr_caps) {

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 818e5d87f0daeb328b47114243a34f348ca874df..34cb25c6166a7f6528b6c6b19ebea0844b8747ed 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1198,6 +1198,11 @@ enum dmub_cmd_type {
         */
        DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
 
+       /**
+        * Command type used for all PSP commands.
+        */
+       DMUB_CMD__PSP = 88,
+
        DMUB_CMD__VBIOS = 128,
 };
 
@@ -4303,6 +4308,65 @@ struct dmub_rb_cmd_secure_display {
        } roi_info;
 };
 
+/**
+ * Command type of a DMUB_CMD__PSP command
+ */
+enum dmub_cmd_psp_type {
+       DMUB_CMD__PSP_ASSR_ENABLE = 0
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.
+ */
+struct dmub_cmd_assr_enable_data {
+       /**
+        * ASSR enable or disable.
+        */
+       uint8_t enable;
+       /**
+        * PHY port type.
+        * Indicates eDP / non-eDP port type
+        */
+       uint8_t phy_port_type;
+       /**
+        * PHY port ID.
+        */
+       uint8_t phy_port_id;
+       /**
+        * Link encoder index.
+        */
+       uint8_t link_enc_index;
+       /**
+        * HPO mode.
+        */
+       uint8_t hpo_mode;
+
+       /**
+        * Reserved field.
+        */
+       uint8_t reserved[7];
+};
+
+/**
+ * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
+ */
+struct dmub_rb_cmd_assr_enable {
+       /**
+        * Command header.
+        */
+       struct dmub_cmd_header header;
+
+       /**
+        * Assr data.
+        */
+       struct dmub_cmd_assr_enable_data assr_data;
+
+       /**
+        * Reserved field.
+        */
+       uint32_t reserved[3];
+};
+
 /**
  * union dmub_rb_cmd - DMUB inbox command.
  */
@@ -4561,6 +4625,10 @@ union dmub_rb_cmd {
         * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
         */
        struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
+       /**
+        * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
+        */
+       struct dmub_rb_cmd_assr_enable assr_enable;
 };
 
 /**