return 0;
 }
 
+void dsi_wait_dsi1_pll_active(void)
+{
+       if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
+               DSSERR("DSI1 PLL clock not active\n");
+}
+
+void dsi_wait_dsi2_pll_active(void)
+{
+       if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
+               DSSERR("DSI2 PLL clock not active\n");
+}
+
 int dsi_init(struct platform_device *pdev)
 {
        u32 rev;
 
 
        b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
 
+       if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
+               dsi_wait_dsi1_pll_active();
+
        REG_FLD_MOD(DSS_CONTROL, b, 0, 0);      /* DISPC_CLK_SWITCH */
 
        dss.dispc_clk_source = clk_src;
 
        b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
 
+       if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
+               dsi_wait_dsi2_pll_active();
+
        REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 
        dss.dsi_clk_source = clk_src;
 
 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
                u32 fifo_size, enum omap_burst_size *burst_size,
                u32 *fifo_low, u32 *fifo_high);
+void dsi_wait_dsi1_pll_active(void);
+void dsi_wait_dsi2_pll_active(void);
 #else
 static inline int dsi_init(struct platform_device *pdev)
 {
 static inline void dsi_exit(void)
 {
 }
+static inline void dsi_wait_dsi1_pll_active(void)
+{
+}
+static inline void dsi_wait_dsi2_pll_active(void)
+{
+}
 #endif
 
 /* DPI */