igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK

Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros.
This prepares the code for adding a new TXDCTL priority field in an
upcoming patch.

Verified that the macro values remain unchanged before and after
refactoring.

Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
Tested-by: Mor Bar-Gabay <morx.bar.gabay@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
index db1e2db1619eb4965850cfae7560278a382a4955..daab06fc3f8003a7cbe412d928790184329b06a9 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -493,13 +493,18 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
 /* Receive Software Flush */
 #define IGC_RXDCTL_SWFLUSH             0x04000000
 
-#define IGC_TXDCTL_PTHRESH             8
-#define IGC_TXDCTL_HTHRESH             1
-#define IGC_TXDCTL_WTHRESH             16
+#define IGC_TXDCTL_PTHRESH_MASK                GENMASK(4, 0)
+#define IGC_TXDCTL_HTHRESH_MASK                GENMASK(12, 8)
+#define IGC_TXDCTL_WTHRESH_MASK                GENMASK(20, 16)
+#define IGC_TXDCTL_QUEUE_ENABLE_MASK   GENMASK(25, 25)
+#define IGC_TXDCTL_SWFLUSH_MASK                GENMASK(26, 26)
+#define IGC_TXDCTL_PTHRESH(x)          FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x))
+#define IGC_TXDCTL_HTHRESH(x)          FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x))
+#define IGC_TXDCTL_WTHRESH(x)          FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x))
 /* Ena specific Tx Queue */
-#define IGC_TXDCTL_QUEUE_ENABLE                0x02000000
+#define IGC_TXDCTL_QUEUE_ENABLE                FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1)
 /* Transmit Software Flush */
-#define IGC_TXDCTL_SWFLUSH             0x04000000
+#define IGC_TXDCTL_SWFLUSH             FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1)
 
 #define IGC_RX_DMA_ATTR \
        (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)

diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
index 4f1a8bc006c619e852cfd93be5fcae9e58253637..f3a312c9413b9b317a48abefdb8f82229797de2d 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc_main.c
+++ b/drivers/net/ethernet/intel/igc/igc_main.c
@@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *adapter,
        wr32(IGC_TDH(reg_idx), 0);
        writel(0, ring->tail);
 
-       txdctl |= IGC_TXDCTL_PTHRESH;
-       txdctl |= IGC_TXDCTL_HTHRESH << 8;
-       txdctl |= IGC_TXDCTL_WTHRESH << 16;
+       txdctl |= IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) |
+                 IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE;
 
-       txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
        wr32(IGC_TXDCTL(reg_idx), txdctl);
 }