drm/amd/display: polling vid stream status in hpo dp blank

[why]
vid stream control is double bufferred, if we don't wait for video
stream enable set to 0, we may get temporary image corruption
showing on the stream when setting PIXEL_TO_SYMBOL_FIFO_ENABLE to 0.

Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
index 23621ff08c9053c781e93ddcb9904522f5301b07..52fb2bf3d57818c18d2774d9f540d923da149f8d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
@@ -150,9 +150,9 @@ static void dcn31_hpo_dp_stream_enc_dp_blank(
         * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
         * a little more because we may not trust delay accuracy.
         */
-       //REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL,
-       //              VID_STREAM_STATUS, 0,
-       //              10, 5000);
+       REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL,
+                       VID_STREAM_STATUS, 0,
+                       10, 5000);
 
        /* Disable SDP tranmission */
        REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,