if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
                return;
 
+       adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD;
        u64_stats_update_begin(&adapter->syncp);
        adapter->dev_stats.tx_timeout++;
        u64_stats_update_end(&adapter->syncp);
        u64_stats_update_end(&tx_ring->syncp);
 
        /* Trigger device reset */
+       tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
        set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
        return -EFAULT;
 }
        u64_stats_update_end(&rx_ring->syncp);
 
        /* Too many desc from the device. Trigger reset */
+       adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS;
        set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
 
        return 0;
        if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
                int rc;
 
-               rc = ena_com_dev_reset(adapter->ena_dev);
+               rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
                if (rc)
                        dev_err(&adapter->pdev->dev, "Device reset failed\n");
        }
        readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
        ena_com_set_mmio_read_mode(ena_dev, readless_supported);
 
-       rc = ena_com_dev_reset(ena_dev);
+       rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
        if (rc) {
                dev_err(dev, "Can not reset device\n");
                goto err_mmio_read_less;
 
        ena_com_mmio_reg_read_request_destroy(ena_dev);
 
+       adapter->reset_reason = ENA_REGS_RESET_NORMAL;
        clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
 
        /* Finish with the destroy part. Start the init part */
                                          "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
                                          missed_tx,
                                          adapter->missing_tx_completion_threshold);
+                               adapter->reset_reason =
+                                       ENA_REGS_RESET_MISS_TX_CMPL;
                                set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
                                return -EIO;
                        }
                u64_stats_update_begin(&adapter->syncp);
                adapter->dev_stats.wd_expired++;
                u64_stats_update_end(&adapter->syncp);
+               adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
                set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
        }
 }
                u64_stats_update_begin(&adapter->syncp);
                adapter->dev_stats.admin_q_pause++;
                u64_stats_update_end(&adapter->syncp);
+               adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
                set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
        }
 }
        ena_set_conf_feat_params(adapter, &get_feat_ctx);
 
        adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
+       adapter->reset_reason = ENA_REGS_RESET_NORMAL;
 
        adapter->tx_ring_size = queue_size;
        adapter->rx_ring_size = queue_size;
        ena_com_delete_debug_area(ena_dev);
        ena_com_rss_destroy(ena_dev);
 err_free_msix:
-       ena_com_dev_reset(ena_dev);
+       ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR);
        ena_free_mgmnt_irq(adapter);
        pci_free_irq_vectors(adapter->pdev);
 err_worker_destroy:
 
        /* Reset the device only if the device is running. */
        if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
-               ena_com_dev_reset(ena_dev);
+               ena_com_dev_reset(ena_dev, adapter->reset_reason);
 
        ena_free_mgmnt_irq(adapter);
 
 
 #ifndef _ENA_REGS_H_
 #define _ENA_REGS_H_
 
+enum ena_regs_reset_reason_types {
+       ENA_REGS_RESET_NORMAL                   = 0,
+
+       ENA_REGS_RESET_KEEP_ALIVE_TO            = 1,
+
+       ENA_REGS_RESET_ADMIN_TO                 = 2,
+
+       ENA_REGS_RESET_MISS_TX_CMPL             = 3,
+
+       ENA_REGS_RESET_INV_RX_REQ_ID            = 4,
+
+       ENA_REGS_RESET_INV_TX_REQ_ID            = 5,
+
+       ENA_REGS_RESET_TOO_MANY_RX_DESCS        = 6,
+
+       ENA_REGS_RESET_INIT_ERR                 = 7,
+
+       ENA_REGS_RESET_DRIVER_INVALID_STATE     = 8,
+
+       ENA_REGS_RESET_OS_TRIGGER               = 9,
+
+       ENA_REGS_RESET_OS_NETDEV_WD             = 10,
+
+       ENA_REGS_RESET_SHUTDOWN                 = 11,
+
+       ENA_REGS_RESET_USER_TRIGGER             = 12,
+
+       ENA_REGS_RESET_GENERIC                  = 13,
+};
+
 /* ena_registers offsets */
 #define ENA_REGS_VERSION_OFF           0x0
 #define ENA_REGS_CONTROLLER_VERSION_OFF                0x4
 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK                0x4
 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT               3
 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK                0x8
+#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT            28
+#define ENA_REGS_DEV_CTL_RESET_REASON_MASK             0xf0000000
 
 /* dev_sts register */
 #define ENA_REGS_DEV_STS_READY_MASK            0x1