]> www.infradead.org Git - users/willy/xarray.git/commitdiff
arm64: dts: imx8-apalis: Add PCIe and SATA support
authorMax Krummenacher <max.krummenacher@toradex.com>
Wed, 16 Apr 2025 15:13:41 +0000 (17:13 +0200)
committerShawn Guo <shawnguo@kernel.org>
Fri, 25 Apr 2025 03:02:53 +0000 (11:02 +0800)
The needed drivers to support PCIe and SATA for i.MX 8QM have been
added.
Configure them for the Apalis iMX8 SoM.

The pciea and pcieb blocks each get a single PCIe lane, pciea is
available on the carrier boards while pcieb is connected to the
on module Wi-Fi/BT module.
The SATA lane is available on the carrier boards.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi

index dc127298715b3cf73ad93d25aff7b7b56e4049ab..311d4950793cff168507be70e4ed71fe988c9679 100644 (file)
        status = "okay";
 };
 
-/* TODO: Apalis PCIE1 */
+/* Apalis PCIE1 */
+&pciea {
+       status = "okay";
+};
 
 /* TODO: Apalis BKL1_PWM */
 
        status = "okay";
 };
 
-/* TODO: Apalis SATA1 */
+/* Apalis SATA1 */
+&sata {
+       status = "okay";
+};
 
 /* Apalis SPDIF1 */
 &spdif0 {
index d4a1ad528f650d16e9de22e2e21d2e2cc684163e..3d8731504ce15c616492c595c254c4ec6dc76bf9 100644 (file)
        status = "okay";
 };
 
-/* TODO: Apalis PCIE1 */
+/* Apalis PCIE1 */
+&pciea {
+       status = "okay";
+};
 
 /* TODO: Apalis BKL1_PWM */
 
        status = "okay";
 };
 
-/* TODO: Apalis SATA1 */
+/* Apalis SATA1 */
+&sata {
+       status = "okay";
+};
 
 /* Apalis SPDIF1 */
 &spdif0 {
index 5e132c83e1b26b19840aac12d2c1014811c75c78..106e802a68ba582e3872e83ea6d9fdb3f1823cd4 100644 (file)
        status = "okay";
 };
 
-/* TODO: Apalis PCIE1 */
+/* Apalis PCIE1 */
+&pciea {
+       status = "okay";
+};
 
 /* TODO: Apalis BKL1_PWM */
 
        status = "okay";
 };
 
-/* TODO: Apalis SATA1 */
+/* Apalis SATA1 */
+&sata {
+       status = "okay";
+};
 
 /* Apalis SPDIF1 */
 &spdif0 {
index dbea1eefdeecf12895674bf2e63a088058d4a5f7..6f27a9cc249461aef34705bf1cada3fe215f1060 100644 (file)
        pinctrl-0 = <&pinctrl_flexcan3>;
 };
 
+&hsio_phy {
+       fsl,hsio-cfg = "pciea-pcieb-sata";
+       fsl,refclk-pad-mode = "input";
+       status = "okay";
+};
+
+&hsio_refa_clk {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
+       enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>;
+};
+
+&hsio_refb_clk {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
+       clocks = <&hsio_refa_clk>;
+       enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>;
+};
+
 /* TODO: Apalis HDMI1 */
 
 &gpu_alert0 {
                          "MXM3_112",
                          "MXM3_118",
                          "MXM3_114",
-                         "MXM3_116";
+                         "MXM3_116",
+                         "",
+                         "",
+                         "MXM3_26";
 };
 
 &lsio_gpio1 {
                          "MXM3_183",
                          "MXM3_185",
                          "MXM3_187";
-
-       pcie-wifi-hog {
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
-               gpio-hog;
-               gpios = <11 GPIO_ACTIVE_HIGH>;
-               line-name = "PCIE_WIFI_CLK";
-               output-high;
-       };
 };
 
 &lsio_gpio3 {
                          "MXM3_291",
                          "MXM3_289",
                          "MXM3_287";
-
-       /* Enable pcie root / sata ref clock unconditionally */
-       pcie-sata-hog {
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
-               gpio-hog;
-               gpios = <11 GPIO_ACTIVE_HIGH>;
-               line-name = "PCIE_SATA_CLK";
-               output-high;
-       };
 };
 
 &lsio_gpio5 {
        status = "okay";
 };
 
-/* TODO: Apalis PCIE1 */
+/* Apalis PCIE1 */
+&pciea {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_reset_moci>;
+       phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
+       phy-names = "pcie-phy";
+       reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>;
+       vpcie-supply = <&reg_pcie_switch>;
+};
+
+/* On-module Wi-Fi */
+&pcieb {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>;
+       phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
+       phy-names = "pcie-phy";
+       reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
 
-/* TODO: On-module Wi-Fi */
+&phyx2_lpcg {
+       clocks = <&hsio_refa_clk>, <&hsio_refb_clk>,
+                <&hsio_refa_clk>, <&hsio_per_clk>;
+};
 
 /* TODO: Apalis BKL1_PWM */
 
                               <722534400>, <45158400>, <11289600>, <49152000>;
 };
 
-/* TODO: Apalis SATA1 */
-
 /* Apalis SPDIF1 */
 &spdif0 {
        assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
index c18f57039f6efb09e02a67e0d793c925d1ae96db..f97feee52c8186b55e70a356199cf8c3b933a7f7 100644 (file)
        phy-mode = "rgmii-rxid";
 };
 
+&hsio_refa_clk {
+       enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>;
+};
+
 /* TODO: Apalis HDMI1 */
 
 /* Apalis I2C2 (DDC) */
                          "MXM3_291",
                          "MXM3_289",
                          "MXM3_287";
-
-       /* Enable pcie root / sata ref clock unconditionally */
-       pcie-sata-hog {
-               gpios = <27 GPIO_ACTIVE_HIGH>;
-       };
-
 };
 
 &lsio_gpio5 {