arm64: dts: rockchip: fixes PHY reset for Lunzn Fastrhino R68S

Fixed the PHY address and reset GPIOs (does not match the corresponding
pinctrl) for gmac0 and gmac1.

Fixes: b9f8ca655d80 ("arm64: dts: rockchip: Add Lunzn Fastrhino R68S")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20240630150010.55729-7-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
index a3339186e89c874b9e2fac2d5aef466f3674c10c..ce2a5e1ccefc3f7d54042cefed90af1f652382f3 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
@@ -39,7 +39,7 @@
                     &gmac0_rx_bus2
                     &gmac0_rgmii_clk
                     &gmac0_rgmii_bus>;
-       snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
+       snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        /* Reset time is 15ms, 50ms for rtl8211f */
        snps,reset-delays-us = <0 15000 50000>;
@@ -61,7 +61,7 @@
                     &gmac1m1_rx_bus2
                     &gmac1m1_rgmii_clk
                     &gmac1m1_rgmii_bus>;
-       snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
+       snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        /* Reset time is 15ms, 50ms for rtl8211f */
        snps,reset-delays-us = <0 15000 50000>;
@@ -71,18 +71,18 @@
 };
 
 &mdio0 {
-       rgmii_phy0: ethernet-phy@0 {
+       rgmii_phy0: ethernet-phy@1 {
                compatible = "ethernet-phy-ieee802.3-c22";
-               reg = <0>;
+               reg = <0x1>;
                pinctrl-0 = <&eth_phy0_reset_pin>;
                pinctrl-names = "default";
        };
 };
 
 &mdio1 {
-       rgmii_phy1: ethernet-phy@0 {
+       rgmii_phy1: ethernet-phy@1 {
                compatible = "ethernet-phy-ieee802.3-c22";
-               reg = <0>;
+               reg = <0x1>;
                pinctrl-0 = <&eth_phy1_reset_pin>;
                pinctrl-names = "default";
        };