};
                };
 
-               target-module@31000 {                   /* 0x44e31000, ap 25 40.0 */
+               timer1_target: target-module@31000 {    /* 0x44e31000, ap 25 40.0 */
                        compatible = "ti,sysc-omap2-timer", "ti,sysc";
-                       ti,hwmods = "timer1";
                        reg = <0x31000 0x4>,
                              <0x31010 0x4>,
                              <0x31014 0x4>;
                        };
                };
 
-               target-module@40000 {                   /* 0x48040000, ap 22 1e.0 */
+               timer2_target: target-module@40000 {    /* 0x48040000, ap 22 1e.0 */
                        compatible = "ti,sysc-omap4-timer", "ti,sysc";
-                       ti,hwmods = "timer2";
                        reg = <0x40000 0x4>,
                              <0x40010 0x4>,
                              <0x40014 0x4>;
 
                #reset-cells = <1>;
        };
 };
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+       ti,no-reset-on-init;
+       ti,no-idle;
+       timer@0 {
+               assigned-clocks = <&timer1_fck>;
+               assigned-clock-parents = <&sys_clkin_ck>;
+       };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+       ti,no-reset-on-init;
+       ti,no-idle;
+       timer@0 {
+               assigned-clocks = <&timer2_fck>;
+               assigned-clock-parents = <&sys_clkin_ck>;
+       };
+};
 
        .init_early     = am33xx_init_early,
        .init_machine   = omap_generic_init,
        .init_late      = am33xx_init_late,
-       .init_time      = omap3_gptimer_timer_init,
+       .init_time      = omap_init_time_of,
        .dt_compat      = am33xx_boards_compat,
        .restart        = am33xx_restart,
 MACHINE_END
 
 
 static void omap_hwmod_am33xx_clkctrl(void)
 {
-       CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_smartreflex0_hwmod,
                AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_smartreflex1_hwmod,
                AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
-       CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
        PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 
        .user           = OCP_USER_MPU,
 };
 
-/* l4 wkup -> timer1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
-       .master         = &am33xx_l4_wkup_hwmod,
-       .slave          = &am33xx_timer1_hwmod,
-       .clk            = "dpll_core_m4_div2_ck",
-       .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l3_main__emif,
        &am33xx_mpu__l3_main,
        &am33xx_l4_wkup__control,
        &am33xx_l4_wkup__smartreflex0,
        &am33xx_l4_wkup__smartreflex1,
-       &am33xx_l4_wkup__timer1,
        &am33xx_l4_wkup__rtc,
-       &am33xx_l4_ls__timer2,
        &am33xx_l3_s__gpmc,
        &am33xx_l3_main__ocmc,
        NULL,