* @user_interrupt_count: number of user interrupts.
  * @user_dec_intr_count: number of decoder interrupts exposed to user.
  * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host.
+ * @unexpected_user_error_interrupt_id: interrupt id used to indicate an unexpected user error.
  * @cache_line_size: device cache line size.
  * @server_type: Server type that the ASIC is currently installed in.
  *               The value is according to enum hl_server_type in uapi file.
        u16                             user_interrupt_count;
        u16                             user_dec_intr_count;
        u16                             tpc_interrupt_id;
+       u16                             unexpected_user_error_interrupt_id;
        u16                             cache_line_size;
        u16                             server_type;
        u8                              completion_queues_count;
 enum hl_user_interrupt_type {
        HL_USR_INTERRUPT_CQ = 0,
        HL_USR_INTERRUPT_DECODER,
-       HL_USR_INTERRUPT_TPC
+       HL_USR_INTERRUPT_TPC,
+       HL_USR_INTERRUPT_UNEXPECTED
 };
 
 /**
  *                  interrupt, driver will monitor the list of fences
  *                  registered to this interrupt.
  * @tpc_interrupt: single TPC interrupt for all TPCs.
+ * @unexpected_error_interrupt: single interrupt for unexpected user error indication.
  * @common_user_cq_interrupt: common user CQ interrupt for all user CQ interrupts.
  *                         upon any user CQ interrupt, driver will monitor the
  *                         list of fences registered to this common structure.
        struct hl_cq                    *completion_queue;
        struct hl_user_interrupt        *user_interrupt;
        struct hl_user_interrupt        tpc_interrupt;
+       struct hl_user_interrupt        unexpected_error_interrupt;
        struct hl_user_interrupt        common_user_cq_interrupt;
        struct hl_user_interrupt        common_decoder_interrupt;
        struct hl_cs                    **shadow_cs_queue;
 
 
        prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
        prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT;
+       prop->unexpected_user_error_interrupt_id = GAUDI2_IRQ_NUM_UNEXPECTED_ERROR;
 
        prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER;
 
        /* Initialize TPC interrupt */
        HL_USR_INTR_STRUCT_INIT(hdev->tpc_interrupt, hdev, 0, HL_USR_INTERRUPT_TPC);
 
+       /* Initialize general purpose interrupt */
+       HL_USR_INTR_STRUCT_INIT(hdev->unexpected_error_interrupt, hdev, 0,
+                                               HL_USR_INTERRUPT_UNEXPECTED);
+
        /* Initialize common user CQ interrupt */
        HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev,
                                HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ);
                return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM];
        case GAUDI2_IRQ_NUM_TPC_ASSERT:
                return "gaudi2 tpc assert";
+       case GAUDI2_IRQ_NUM_UNEXPECTED_ERROR:
+               return "gaudi2 tpc assert";
        case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST:
                return "gaudi2 user completion";
        default:
                goto free_dec_irq;
        }
 
+       irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
+       rc = request_irq(irq, hl_irq_handler_user_interrupt, 0,
+                       gaudi2_irq_name(GAUDI2_IRQ_NUM_UNEXPECTED_ERROR),
+                                       &hdev->unexpected_error_interrupt);
+       if (rc) {
+               dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+               goto free_tpc_irq;
+       }
+
        for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0;
                        user_irq_init_cnt < prop->user_interrupt_count;
                        i++, j++, user_irq_init_cnt++) {
                irq = pci_irq_vector(hdev->pdev, i);
                free_irq(irq, &hdev->user_interrupt[j]);
        }
+       irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
+       free_irq(irq, &hdev->unexpected_error_interrupt);
+free_tpc_irq:
+       irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
+       free_irq(irq, &hdev->tpc_interrupt);
 free_dec_irq:
        gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_DEC_LAST + 1);
 free_event_irq:
        }
 
        synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT));
+       synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR));
 
        for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
                                                                                i++, j++) {
        irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
        free_irq(irq, &hdev->tpc_interrupt);
 
+       irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
+       free_irq(irq, &hdev->unexpected_error_interrupt);
+
        for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
                        k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
 
 
  * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode
  */
 #define GAUDI2_NUM_USER_INTERRUPTS 255
+#define GAUDI2_NUM_RESERVED_INTERRUPTS 1
+#define GAUDI2_TOTAL_USER_INTERRUPTS (GAUDI2_NUM_USER_INTERRUPTS + GAUDI2_NUM_RESERVED_INTERRUPTS)
 
 enum gaudi2_irq_num {
        GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX,
        GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
        GAUDI2_IRQ_NUM_TPC_ASSERT,
        GAUDI2_IRQ_NUM_RESERVED_FIRST,
-       GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_USER_INTERRUPTS - 1),
-       GAUDI2_IRQ_NUM_USER_FIRST,
+       GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_TOTAL_USER_INTERRUPTS - 1),
+       GAUDI2_IRQ_NUM_UNEXPECTED_ERROR = RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT,
+       GAUDI2_IRQ_NUM_USER_FIRST = GAUDI2_IRQ_NUM_UNEXPECTED_ERROR + 1,
        GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
        GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
 };