KVM: SVM: Add support for SEV-ES GHCB MSR protocol function 0x100

The GHCB specification defines a GHCB MSR protocol using the lower
12-bits of the GHCB MSR (in the hypervisor this corresponds to the
GHCB GPA field in the VMCB).

Function 0x100 is a request for termination of the guest. The guest has
encountered some situation for which it has requested to be terminated.
The GHCB MSR value contains the reason for the request.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <f3a1f7850c75b6ea4101e15bbb4a3af1a203f1dc.1607620209.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index fbb80b58284338450a12c096d7f8ec341cc87375..db123562e7d50e9d36b09915e1e66d6394cef0bc 100644 (file)
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -1570,6 +1570,19 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm)
                                  GHCB_MSR_INFO_POS);
                break;
        }
+       case GHCB_MSR_TERM_REQ: {
+               u64 reason_set, reason_code;
+
+               reason_set = get_ghcb_msr_bits(svm,
+                                              GHCB_MSR_TERM_REASON_SET_MASK,
+                                              GHCB_MSR_TERM_REASON_SET_POS);
+               reason_code = get_ghcb_msr_bits(svm,
+                                               GHCB_MSR_TERM_REASON_MASK,
+                                               GHCB_MSR_TERM_REASON_POS);
+               pr_info("SEV-ES guest requested termination: %#llx:%#llx\n",
+                       reason_set, reason_code);
+               fallthrough;
+       }
        default:
                ret = -EINVAL;
        }

diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 9dd8429f2b276a2c2b6f5b17444859497298ddd0..fc69bc2e0cad771feebece3911b940d7fdca13e9 100644 (file)
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -543,6 +543,12 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
 #define GHCB_MSR_CPUID_REG_POS         30
 #define GHCB_MSR_CPUID_REG_MASK                0x3
 
+#define GHCB_MSR_TERM_REQ              0x100
+#define GHCB_MSR_TERM_REASON_SET_POS   12
+#define GHCB_MSR_TERM_REASON_SET_MASK  0xf
+#define GHCB_MSR_TERM_REASON_POS       16
+#define GHCB_MSR_TERM_REASON_MASK      0xff
+
 extern unsigned int max_sev_asid;
 
 static inline bool svm_sev_enabled(void)