* Use PCH_NOP (PCH but no South Display) for PCH platforms without
         * display.
         */
-       if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
+       if (pch && !HAS_DISPLAY(dev_priv)) {
                DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
                dev_priv->pch_type = PCH_NOP;
                dev_priv->pch_id = 0;
        if (i915_inject_load_failure())
                return -ENODEV;
 
-       if (INTEL_INFO(dev_priv)->num_pipes) {
+       if (HAS_DISPLAY(dev_priv)) {
                ret = drm_vblank_init(&dev_priv->drm,
                                      INTEL_INFO(dev_priv)->num_pipes);
                if (ret)
 
        intel_overlay_setup(dev_priv);
 
-       if (INTEL_INFO(dev_priv)->num_pipes == 0)
+       if (!HAS_DISPLAY(dev_priv))
                return 0;
 
        ret = intel_fbdev_init(dev);
        } else
                DRM_ERROR("Failed to register driver for userspace access!\n");
 
-       if (INTEL_INFO(dev_priv)->num_pipes) {
+       if (HAS_DISPLAY(dev_priv)) {
                /* Must be done after probing outputs */
                intel_opregion_register(dev_priv);
                acpi_video_register();
         * We need to coordinate the hotplugs with the asynchronous fbdev
         * configuration, for which we use the fbdev->async_cookie.
         */
-       if (INTEL_INFO(dev_priv)->num_pipes)
+       if (HAS_DISPLAY(dev_priv))
                drm_kms_helper_poll_init(dev);
 
        intel_power_domains_enable(dev_priv);
 
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
+#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
+
 #include "i915_trace.h"
 
 static inline bool intel_vtd_active(void)
 
        const struct bdb_header *bdb;
        u8 __iomem *bios = NULL;
 
-       if (INTEL_INFO(dev_priv)->num_pipes == 0) {
+       if (!HAS_DISPLAY(dev_priv)) {
                DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
                return;
        }
 
        if (i915_modparams.disable_display) {
                DRM_INFO("Display disabled (module parameter)\n");
                info->num_pipes = 0;
-       } else if (info->num_pipes > 0 &&
+       } else if (HAS_DISPLAY(dev_priv) &&
                   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
                   HAS_PCH_SPLIT(dev_priv)) {
                u32 fuse_strap = I915_READ(FUSE_STRAP);
                        DRM_INFO("PipeC fused off\n");
                        info->num_pipes -= 1;
                }
-       } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
+       } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
                u32 dfsm = I915_READ(SKL_DFSM);
                u8 disabled_mask = 0;
                bool invalid;
 
 
        intel_pps_init(dev_priv);
 
-       if (INTEL_INFO(dev_priv)->num_pipes == 0)
+       if (!HAS_DISPLAY(dev_priv))
                return;
 
        /*
        };
        int i;
 
-       if (INTEL_INFO(dev_priv)->num_pipes == 0)
+       if (!HAS_DISPLAY(dev_priv))
                return NULL;
 
        error = kzalloc(sizeof(*error), GFP_ATOMIC);
 
        struct intel_fbdev *ifbdev;
        int ret;
 
-       if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+       if (WARN_ON(!HAS_DISPLAY(dev_priv)))
                return -ENODEV;
 
        ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
 
        unsigned int pin;
        int ret;
 
-       if (INTEL_INFO(dev_priv)->num_pipes == 0)
+       if (!HAS_DISPLAY(dev_priv))
                return 0;
 
        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))