clk: renesas: r9a07g043: Add GbEthernet clock/reset

Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index b9011bc7fe49198a61de608ccd5bd860fe294fdb..03a00ec5ebf3aa287cbf966e206dca2bf4dbc622 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -111,6 +111,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
                                0x52c, 0),
        DEF_MOD("dmac_pclk",    R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
                                0x52c, 1),
+       DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
+                               0x57c, 0),
+       DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
+                               0x57c, 0),
+       DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
+                               0x57c, 1),
+       DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
+                               0x57c, 1),
        DEF_MOD("scif0",        R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
                                0x584, 0),
        DEF_MOD("scif1",        R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
@@ -135,6 +143,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
        DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
        DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
        DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
+       DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
+       DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
        DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
        DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
        DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),