ARM: tegra: apalis-tk1: reorder cpu dfll clock properties

Reorder CPU DFLL clock properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 37e443e21ce638a0277bbd370ea8e23b597af180..07dd208296d3633982a1191a862f47eaedf3be9d 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -1925,8 +1925,8 @@
        /* CPU DFLL clock */
        clock@70110000 {
                status = "okay";
-               vdd-cpu-supply = <&reg_vdd_cpu>;
                nvidia,i2c-fs-rate = <400000>;
+               vdd-cpu-supply = <&reg_vdd_cpu>;
        };
 
        ahub@70300000 {

diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index f76580f6cc80145b14fb937fd93e44d6872b7941..fe10c518076834e2cc66f1d9e936b007c91dd13e 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1954,8 +1954,8 @@
        /* CPU DFLL clock */
        clock@70110000 {
                status = "okay";
-               vdd-cpu-supply = <&reg_vdd_cpu>;
                nvidia,i2c-fs-rate = <400000>;
+               vdd-cpu-supply = <&reg_vdd_cpu>;
        };
 
        ahub@70300000 {