__func__, ret);
goto out;
}
+
+ hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true,
+ AZX_REG_ML_LEPTR_ID_SDW, true);
}
*shim_mask |= BIT(link_id);
*shim_mask &= ~BIT(link_id);
+ if (!*shim_mask)
+ hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true,
+ AZX_REG_ML_LEPTR_ID_SDW, false);
+
ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id);
if (ret < 0) {
dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n",
static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
{
- const struct sof_intel_dsp_desc *chip;
int ret;
/* display codec must be powered before link reset */
hda_dsp_ctrl_ppcap_int_enable(sdev, true);
}
- chip = get_chip_info(sdev->pdata);
- if (chip && chip->hw_ip_version >= SOF_INTEL_ACE_2_0)
- hda_sdw_int_enable(sdev, true);
-
cleanup:
/* display codec can powered off after controller init */
hda_codec_i915_display_power(sdev, false);
return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
}
-static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
-{
- struct hdac_bus *bus = sof_to_bus(sdev);
-
- hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable);
-}
-
static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{
- lnl_enable_sdw_irq(sdev, false);
mtl_disable_ipc_interrupts(sdev);
return mtl_enable_interrupts(sdev, false);
}
.ssp_count = MTL_SSP_COUNT,
.d0i3_offset = MTL_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_ext,
- .enable_sdw_irq = lnl_enable_sdw_irq,
.check_sdw_irq = lnl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.ssp_count = MTL_SSP_COUNT,
.d0i3_offset = MTL_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_ext,
- .enable_sdw_irq = lnl_enable_sdw_irq,
.check_sdw_irq = lnl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
.check_ipc_irq = mtl_dsp_check_ipc_irq,