This improves RX diversity and performance for AR9485.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
                        else
                                value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
 
+                       if (ah->config.alt_mingainidx)
+                               REG_RMW_FIELD(ah, AR_PHY_EXT_ATTEN_CTL_0,
+                                             AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
+                                             value);
+
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
                                      value);
 
 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S   28
 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
 #define AR_PHY_EXT_CCA_THRESH62_S       16
+#define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX    0x0000FF00
+#define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX_S  8
 #define AR_PHY_EXT_MINCCA_PWR   0x01FF0000
 #define AR_PHY_EXT_MINCCA_PWR_S 16
 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
 
        u32 xlna_gpio;
        u32 ant_ctrl_comm2g_switch_enable;
        bool xatten_margin_cfg;
+       bool alt_mingainidx;
 };
 
 enum ath9k_int {
 
                               ATH9K_PCI_CUS230)) {
                ah->config.xlna_gpio = 9;
                ah->config.xatten_margin_cfg = true;
+               ah->config.alt_mingainidx = true;
                ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
                sc->ant_comb.low_rssi_thresh = 20;
                sc->ant_comb.fast_div_bias = 3;