clk: at91: clk-master: Add check for divide by 3

A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>

diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 7a544e429d34ea5fbeecc0e29a2da51e0fb49094..d5ea2069ec83a3ef66dcddf15796579b3106a6bd 100644 (file)
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
 {
        struct clk_master *master = to_clk_master(hw);
 
+       if (master->div == MASTER_PRES_MAX)
+               return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
+
        return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
 }