drm/amdgpu/gfx7: enable cp/rlc ints after we disable clockgating

Even if we disable clockgating, we still need to make sure the
cp/rlc interrupts are enabled for powergating which might still
be enabled.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index ee2f2139e2eba62b31173052c7b809c152489585..29d0df2b55d9d78e80508e49b3a8dca61b089ab8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3797,6 +3797,9 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
                gfx_v7_0_update_rlc(adev, tmp);
 
                data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+               if (orig != data)
+                       WREG32(mmRLC_CGCG_CGLS_CTRL, data);
+
        } else {
                gfx_v7_0_enable_gui_idle_interrupt(adev, false);
 
@@ -3806,11 +3809,11 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
                RREG32(mmCB_CGTT_SCLK_CTRL);
 
                data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
-       }
-
-       if (orig != data)
-               WREG32(mmRLC_CGCG_CGLS_CTRL, data);
+               if (orig != data)
+                       WREG32(mmRLC_CGCG_CGLS_CTRL, data);
 
+               gfx_v7_0_enable_gui_idle_interrupt(adev, true);
+       }
 }
 
 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)