if (apiexcp & CECC_EXCP_DETECTED) {
                cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n");
                channel = cpc925_mc_find_channel(mci, syndrome);
-               edac_mc_handle_ce(mci, pfn, offset, syndrome,
-                                 csrow, channel, mci->ctl_name);
+               edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+                                    pfn, offset, syndrome,
+                                    csrow, channel, -1,
+                                    mci->ctl_name, "", NULL);
        }
 
        if (apiexcp & UECC_EXCP_DETECTED) {
                cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n");
-               edac_mc_handle_ue(mci, pfn, offset, csrow, mci->ctl_name);
+               edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+                                    pfn, offset, 0,
+                                    csrow, -1, -1,
+                                    mci->ctl_name, "", NULL);
        }
 
        cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n");
 {
        static int edac_mc_idx;
        struct mem_ctl_info *mci;
+       struct edac_mc_layer layers[2];
        void __iomem *vbase;
        struct cpc925_mc_pdata *pdata;
        struct resource *r;
        }
 
        nr_channels = cpc925_mc_get_channels(vbase) + 1;
-       mci = edac_mc_alloc(sizeof(struct cpc925_mc_pdata),
-                       CPC925_NR_CSROWS, nr_channels, edac_mc_idx);
+
+       layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+       layers[0].size = CPC925_NR_CSROWS;
+       layers[0].is_virt_csrow = true;
+       layers[1].type = EDAC_MC_LAYER_CHANNEL;
+       layers[1].size = nr_channels;
+       layers[1].is_virt_csrow = false;
+       mci = new_edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
+                           sizeof(struct cpc925_mc_pdata));
        if (!mci) {
                cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n");
                res = -ENOMEM;