/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
 
-static void s3c_irq_timer_mask(unsigned int irq)
+static void s3c_irq_timer_mask(struct irq_data *data)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+       u32 mask = (u32)data->chip_data;
 
        reg &= 0x1f;  /* mask out pending interrupts */
-       reg &= ~(1 << (irq - IRQ_TIMER0));
+       reg &= ~mask;
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
-static void s3c_irq_timer_unmask(unsigned int irq)
+static void s3c_irq_timer_unmask(struct irq_data *data)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+       u32 mask = (u32)data->chip_data;
 
        reg &= 0x1f;  /* mask out pending interrupts */
-       reg |= 1 << (irq - IRQ_TIMER0);
+       reg |= mask;
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
-static void s3c_irq_timer_ack(unsigned int irq)
+static void s3c_irq_timer_ack(struct irq_data *data)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+       u32 mask = (u32)data->chip_data;
 
        reg &= 0x1f;
-       reg |= (1 << 5) << (irq - IRQ_TIMER0);
+       reg |= mask << 5;
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
 static struct irq_chip s3c_irq_timer = {
        .name           = "s3c-timer",
-       .mask           = s3c_irq_timer_mask,
-       .unmask         = s3c_irq_timer_unmask,
-       .ack            = s3c_irq_timer_ack,
+       .irq_mask       = s3c_irq_timer_mask,
+       .irq_unmask     = s3c_irq_timer_unmask,
+       .irq_ack        = s3c_irq_timer_ack,
 };
 
 /**
        set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
 
        set_irq_chip(timer_irq, &s3c_irq_timer);
+       set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
        set_irq_handler(timer_irq, handle_level_irq);
        set_irq_flags(timer_irq, IRQF_VALID);