drm/amdgpu: add sdma ip block for navy_flounder

Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 832117939c03bd45a8e57c005341fc169e2b63f1..c8e68de43b129df8616f1bcdd7dc07eaf8e80dc4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -528,6 +528,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
                amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
                amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
                amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
                break;
        default:
                return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index de8342283fdbadc45825878bf54fa446661805f4..46a9617fee5f4135f476e5c7d78759c509db72aa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -45,6 +45,7 @@
 #include "sdma_v5_2.h"
 
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
 
 #define SDMA1_REG_OFFSET 0x600
 #define SDMA3_REG_OFFSET 0x400
@@ -85,6 +86,7 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                break;
        default:
                break;
@@ -152,6 +154,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
        case CHIP_SIENNA_CICHLID:
                chip_name = "sienna_cichlid";
                break;
+       case CHIP_NAVY_FLOUNDER:
+               chip_name = "navy_flounder";
+               break;
        default:
                BUG();
        }
@@ -167,7 +172,8 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
                goto out;
 
        for (i = 1; i < adev->sdma.num_instances; i++) {
-               if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+               if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+                   adev->asic_type == CHIP_NAVY_FLOUNDER) {
                        memcpy((void*)&adev->sdma.instance[i],
                               (void*)&adev->sdma.instance[0],
                               sizeof(struct amdgpu_sdma_instance));
@@ -1155,7 +1161,16 @@ static int sdma_v5_2_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       adev->sdma.num_instances = 4;
+       switch (adev->asic_type) {
+       case CHIP_SIENNA_CICHLID:
+               adev->sdma.num_instances = 4;
+               break;
+       case CHIP_NAVY_FLOUNDER:
+               adev->sdma.num_instances = 2;
+               break;
+       default:
+               break;
+       }
 
        sdma_v5_2_set_ring_funcs(adev);
        sdma_v5_2_set_buffer_funcs(adev);
@@ -1548,6 +1563,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
 
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                sdma_v5_2_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                sdma_v5_2_update_medium_grain_light_sleep(adev,