s390/cpumf: Update CPU Measurement facility extended counter set support

Update CPU Measurement counter facility support for the
extended counter set for machine types 9175 and 9176.

Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>

diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c
index 33205dd410e4700a4c84bd3cc2a5f6e579ae30ef..fe588bfb23e5eb16d3fc4c3ed00dbf484da345f1 100644 (file)
--- a/arch/s390/kernel/perf_cpum_cf.c
+++ b/arch/s390/kernel/perf_cpum_cf.c
@@ -442,7 +442,7 @@ static void cpum_cf_make_setsize(enum cpumf_ctr_set ctrset)
                        ctrset_size = 48;
                else if (cpumf_ctr_info.csvn >= 3 && cpumf_ctr_info.csvn <= 5)
                        ctrset_size = 128;
-               else if (cpumf_ctr_info.csvn == 6 || cpumf_ctr_info.csvn == 7)
+               else if (cpumf_ctr_info.csvn >= 6 && cpumf_ctr_info.csvn <= 8)
                        ctrset_size = 160;
                break;
        case CPUMF_CTR_SET_MT_DIAG:

diff --git a/arch/s390/kernel/perf_cpum_cf_events.c b/arch/s390/kernel/perf_cpum_cf_events.c
index e4a6bfc910808a9ef98a208cff2f24f75eaf60ed..690a293eb10d635b9ff250e1e3339474ff7a64aa 100644 (file)
--- a/arch/s390/kernel/perf_cpum_cf_events.c
+++ b/arch/s390/kernel/perf_cpum_cf_events.c
@@ -237,7 +237,6 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
-
 CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
 CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
 CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
@@ -365,6 +364,83 @@ CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
 CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
 CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
 CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
+CPUMF_EVENT_ATTR(cf_z17, L1D_RO_EXCL_WRITES, 0x0080);
+CPUMF_EVENT_ATTR(cf_z17, DTLB2_WRITES, 0x0081);
+CPUMF_EVENT_ATTR(cf_z17, DTLB2_MISSES, 0x0082);
+CPUMF_EVENT_ATTR(cf_z17, CRSTE_1MB_WRITES, 0x0083);
+CPUMF_EVENT_ATTR(cf_z17, DTLB2_GPAGE_WRITES, 0x0084);
+CPUMF_EVENT_ATTR(cf_z17, ITLB2_WRITES, 0x0086);
+CPUMF_EVENT_ATTR(cf_z17, ITLB2_MISSES, 0x0087);
+CPUMF_EVENT_ATTR(cf_z17, TLB2_PTE_WRITES, 0x0089);
+CPUMF_EVENT_ATTR(cf_z17, TLB2_CRSTE_WRITES, 0x008a);
+CPUMF_EVENT_ATTR(cf_z17, TLB2_ENGINES_BUSY, 0x008b);
+CPUMF_EVENT_ATTR(cf_z17, TX_C_TEND, 0x008c);
+CPUMF_EVENT_ATTR(cf_z17, TX_NC_TEND, 0x008d);
+CPUMF_EVENT_ATTR(cf_z17, L1C_TLB2_MISSES, 0x008f);
+CPUMF_EVENT_ATTR(cf_z17, DCW_REQ, 0x0091);
+CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_IV, 0x0092);
+CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_CHIP_HIT, 0x0093);
+CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_DRAWER_HIT, 0x0094);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP, 0x0095);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_IV, 0x0096);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_CHIP_HIT, 0x0097);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE, 0x0099);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER, 0x009a);
+CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER, 0x009b);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_MEMORY, 0x009c);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE_MEMORY, 0x009d);
+CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER_MEMORY, 0x009e);
+CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER_MEMORY, 0x009f);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_IV, 0x00a0);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_IV, 0x00a3);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_IV, 0x00a6);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
+CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
+CPUMF_EVENT_ATTR(cf_z17, ICW_REQ, 0x00a9);
+CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_IV, 0x00aa);
+CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_CHIP_HIT, 0x00ab);
+CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_DRAWER_HIT, 0x00ac);
+CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP, 0x00ad);
+CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_IV, 0x00ae);
+CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_CHIP_HIT, 0x00af);
+CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
+CPUMF_EVENT_ATTR(cf_z17, ICW_ON_MODULE, 0x00b1);
+CPUMF_EVENT_ATTR(cf_z17, ICW_ON_DRAWER, 0x00b2);
+CPUMF_EVENT_ATTR(cf_z17, ICW_OFF_DRAWER, 0x00b3);
+CPUMF_EVENT_ATTR(cf_z17, CYCLES_SAMETHRD, 0x00ca);
+CPUMF_EVENT_ATTR(cf_z17, CYCLES_DIFFTHRD, 0x00cb);
+CPUMF_EVENT_ATTR(cf_z17, INST_SAMETHRD, 0x00cc);
+CPUMF_EVENT_ATTR(cf_z17, INST_DIFFTHRD, 0x00cd);
+CPUMF_EVENT_ATTR(cf_z17, WRONG_BRANCH_PREDICTION, 0x00ce);
+CPUMF_EVENT_ATTR(cf_z17, VX_BCD_EXECUTION_SLOTS, 0x00e1);
+CPUMF_EVENT_ATTR(cf_z17, DECIMAL_INSTRUCTIONS, 0x00e2);
+CPUMF_EVENT_ATTR(cf_z17, LAST_HOST_TRANSLATIONS, 0x00e8);
+CPUMF_EVENT_ATTR(cf_z17, TX_NC_TABORT, 0x00f4);
+CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_NO_SPECIAL, 0x00f5);
+CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_SPECIAL, 0x00f6);
+CPUMF_EVENT_ATTR(cf_z17, DFLT_ACCESS, 0x00f8);
+CPUMF_EVENT_ATTR(cf_z17, DFLT_CYCLES, 0x00fd);
+CPUMF_EVENT_ATTR(cf_z17, SORTL, 0x0100);
+CPUMF_EVENT_ATTR(cf_z17, DFLT_CC, 0x0109);
+CPUMF_EVENT_ATTR(cf_z17, DFLT_CCFINISH, 0x010a);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_INVOCATIONS, 0x010b);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPLETIONS, 0x010c);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_WAIT_LOCK, 0x010d);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_HOLD_LOCK, 0x010e);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_ONCHIP, 0x0110);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_OFFCHIP, 0x0111);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_DIFF, 0x0112);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_4K_PREFETCH, 0x0114);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPL_LOCK, 0x0115);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK, 0x0116);
+CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO, 0x0117);
+CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
+CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
 
 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
        CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
@@ -414,7 +490,7 @@ static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
        NULL,
 };
 
-static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = {
+static struct attribute *cpumcf_svn_678_pmu_event_attr[] __initdata = {
        CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
        CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
        CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
@@ -779,6 +855,87 @@ static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
        NULL,
 };
 
+static struct attribute *cpumcf_z17_pmu_event_attr[] __initdata = {
+       CPUMF_EVENT_PTR(cf_z17, L1D_RO_EXCL_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, DTLB2_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, DTLB2_MISSES),
+       CPUMF_EVENT_PTR(cf_z17, CRSTE_1MB_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, DTLB2_GPAGE_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, ITLB2_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, ITLB2_MISSES),
+       CPUMF_EVENT_PTR(cf_z17, TLB2_PTE_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, TLB2_CRSTE_WRITES),
+       CPUMF_EVENT_PTR(cf_z17, TLB2_ENGINES_BUSY),
+       CPUMF_EVENT_PTR(cf_z17, TX_C_TEND),
+       CPUMF_EVENT_PTR(cf_z17, TX_NC_TEND),
+       CPUMF_EVENT_PTR(cf_z17, L1C_TLB2_MISSES),
+       CPUMF_EVENT_PTR(cf_z17, DCW_REQ),
+       CPUMF_EVENT_PTR(cf_z17, DCW_REQ_IV),
+       CPUMF_EVENT_PTR(cf_z17, DCW_REQ_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, DCW_REQ_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_IV),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER),
+       CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_MEMORY),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE_MEMORY),
+       CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER_MEMORY),
+       CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER_MEMORY),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_IV),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_IV),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_IV),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, ICW_REQ),
+       CPUMF_EVENT_PTR(cf_z17, ICW_REQ_IV),
+       CPUMF_EVENT_PTR(cf_z17, ICW_REQ_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, ICW_REQ_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP),
+       CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_IV),
+       CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_CHIP_HIT),
+       CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT),
+       CPUMF_EVENT_PTR(cf_z17, ICW_ON_MODULE),
+       CPUMF_EVENT_PTR(cf_z17, ICW_ON_DRAWER),
+       CPUMF_EVENT_PTR(cf_z17, ICW_OFF_DRAWER),
+       CPUMF_EVENT_PTR(cf_z17, CYCLES_SAMETHRD),
+       CPUMF_EVENT_PTR(cf_z17, CYCLES_DIFFTHRD),
+       CPUMF_EVENT_PTR(cf_z17, INST_SAMETHRD),
+       CPUMF_EVENT_PTR(cf_z17, INST_DIFFTHRD),
+       CPUMF_EVENT_PTR(cf_z17, WRONG_BRANCH_PREDICTION),
+       CPUMF_EVENT_PTR(cf_z17, VX_BCD_EXECUTION_SLOTS),
+       CPUMF_EVENT_PTR(cf_z17, DECIMAL_INSTRUCTIONS),
+       CPUMF_EVENT_PTR(cf_z17, LAST_HOST_TRANSLATIONS),
+       CPUMF_EVENT_PTR(cf_z17, TX_NC_TABORT),
+       CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_NO_SPECIAL),
+       CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_SPECIAL),
+       CPUMF_EVENT_PTR(cf_z17, DFLT_ACCESS),
+       CPUMF_EVENT_PTR(cf_z17, DFLT_CYCLES),
+       CPUMF_EVENT_PTR(cf_z17, SORTL),
+       CPUMF_EVENT_PTR(cf_z17, DFLT_CC),
+       CPUMF_EVENT_PTR(cf_z17, DFLT_CCFINISH),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_INVOCATIONS),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_COMPLETIONS),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_WAIT_LOCK),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_HOLD_LOCK),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_INST_ONCHIP),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_INST_OFFCHIP),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_INST_DIFF),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_4K_PREFETCH),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_COMPL_LOCK),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK),
+       CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO),
+       CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
+       CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
+       NULL,
+};
+
 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
 
 static struct attribute_group cpumcf_pmu_events_group = {
@@ -859,7 +1016,7 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
        if (ci.csvn >= 1 && ci.csvn <= 5)
                csvn = cpumcf_svn_12345_pmu_event_attr;
        else if (ci.csvn >= 6)
-               csvn = cpumcf_svn_67_pmu_event_attr;
+               csvn = cpumcf_svn_678_pmu_event_attr;
 
        /* Determine model-specific counter set(s) */
        get_cpu_id(&cpu_id);
@@ -892,6 +1049,10 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
        case 0x3932:
                model = cpumcf_z16_pmu_event_attr;
                break;
+       case 0x9175:
+       case 0x9176:
+               model = cpumcf_z17_pmu_event_attr;
+               break;
        default:
                model = none;
                break;