pipe_config->fec_enable);
                }
 
+               pipe_config->infoframes.enable |=
+                       intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
                break;
        case TRANS_DDI_MODE_SELECT_DP_MST:
                pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
                                        REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
 
                intel_dp_get_m_n(intel_crtc, pipe_config);
+
+               pipe_config->infoframes.enable |=
+                       intel_hdmi_infoframes_enabled(encoder, pipe_config);
                break;
        default:
                break;
 
        if (INTEL_GEN(dev_priv) >= 8)
                bdw_get_trans_port_sync_config(pipe_config);
+
+       intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
 static enum intel_output_type