assert_rpm_wakelock_held(>->i915->runtime_pm);
 
        spin_lock_irq(>->irq_lock);
-       if (!guc->interrupts.enabled) {
-               WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
-                            gt->pm_guc_events);
-               guc->interrupts.enabled = true;
-               gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
-       }
+       WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+                    gt->pm_guc_events);
+       gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
        spin_unlock_irq(>->irq_lock);
 }
 
        assert_rpm_wakelock_held(>->i915->runtime_pm);
 
        spin_lock_irq(>->irq_lock);
-       guc->interrupts.enabled = false;
 
        gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
 
 static void gen11_enable_guc_interrupts(struct intel_guc *guc)
 {
        struct intel_gt *gt = guc_to_gt(guc);
+       u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
 
        spin_lock_irq(>->irq_lock);
-       if (!guc->interrupts.enabled) {
-               u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
-
-               WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
-               intel_uncore_write(gt->uncore,
-                                  GEN11_GUC_SG_INTR_ENABLE, events);
-               intel_uncore_write(gt->uncore,
-                                  GEN11_GUC_SG_INTR_MASK, ~events);
-               guc->interrupts.enabled = true;
-       }
+       WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
+       intel_uncore_write(gt->uncore,
+                          GEN11_GUC_SG_INTR_ENABLE, events);
+       intel_uncore_write(gt->uncore,
+                          GEN11_GUC_SG_INTR_MASK, ~events);
        spin_unlock_irq(>->irq_lock);
 }
 
        struct intel_gt *gt = guc_to_gt(guc);
 
        spin_lock_irq(>->irq_lock);
-       guc->interrupts.enabled = false;
 
        intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
        intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);