net/mlx4_core: Support more than 64 VFs

We now allow up to 126 VFs. Note though that certain firmware
versions only allow up to 80 VFs. Moreover, old HCAs only support 64 VFs.
In these cases, we limit the maximum number of VFs to 64.

Signed-off-by: Matan Barak <matanb@mellanox.com>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index d2f594fadfbf1463d7af528eddfa98df96db8469..4251f81a0275abe4004f0538f578913bba952cba 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -143,7 +143,8 @@ static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
                [14] = "Ethernet protocol control support",
                [15] = "Ethernet Backplane autoneg support",
                [16] = "CONFIG DEV support",
-               [17] = "Asymmetric EQs support"
+               [17] = "Asymmetric EQs support",
+               [18] = "More than 80 VFs support"
        };
        int i;
 
@@ -860,6 +861,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
        if (field32 & (1 << 20))
                dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
+       if (field32 & (1 << 21))
+               dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
 
        if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
                for (i = 1; i <= dev_cap->num_ports; ++i) {

diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index ebb279060a253f8ea12df71c40880e1b5d14e845..3044f9e623cb0336be273d57fbb6f12ca97e4578 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -2373,6 +2373,24 @@ disable_sriov:
        return dev_flags & ~MLX4_FLAG_MASTER;
 }
 
+enum {
+       MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
+};
+
+static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
+                             int *nvfs)
+{
+       int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
+       /* Checking for 64 VFs as a limitation of CX2 */
+       if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
+           requested_vfs >= 64) {
+               mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
+                        requested_vfs);
+               return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
+       }
+       return 0;
+}
+
 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
                         int total_vfs, int *nvfs, struct mlx4_priv *priv)
 {
@@ -2484,6 +2502,9 @@ slave_start:
                                goto err_fw;
                        }
 
+                       if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
+                               goto err_fw;
+
                        if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
                                u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
                                                                  existing_vfs);
@@ -2512,6 +2533,9 @@ slave_start:
                                mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
                                goto err_fw;
                        }
+
+                       if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
+                               goto err_fw;
                }
        }
 

diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 1c560eb870add463064d9e413d40998ee3cf437e..cf09e65c2901e428e33132489e5bb38240c95be1 100644 (file)
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -95,7 +95,7 @@ enum {
 
 enum {
        MLX4_MAX_NUM_PF         = 16,
-       MLX4_MAX_NUM_VF         = 64,
+       MLX4_MAX_NUM_VF         = 126,
        MLX4_MAX_NUM_VF_P_PORT  = 64,
        MLX4_MFUNC_MAX          = 80,
        MLX4_MAX_EQ_NUM         = 1024,
@@ -190,7 +190,8 @@ enum {
        MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL        = 1LL <<  14,
        MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP    = 1LL <<  15,
        MLX4_DEV_CAP_FLAG2_CONFIG_DEV           = 1LL <<  16,
-       MLX4_DEV_CAP_FLAG2_SYS_EQS              = 1LL <<  17
+       MLX4_DEV_CAP_FLAG2_SYS_EQS              = 1LL <<  17,
+       MLX4_DEV_CAP_FLAG2_80_VFS               = 1LL <<  18
 };
 
 enum {