riscv: hwprobe: add zve Vector subextensions into hwprobe interface

The following Vector subextensions for "embedded" platforms are added
into RISCV_HWPROBE_KEY_IMA_EXT_0:
 - ZVE32X
 - ZVE32F
 - ZVE64X
 - ZVE64F
 - ZVE64D

Extensions ending with an X indicates that the platform doesn't have a
vector FPU.
Extensions ending with F/D mean that whether single (F) or double (D)
precision vector operation is supported.
The number 32 or 64 follows from ZVE tells the maximum element length.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-6-0711bdd26c12@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 204cd4433af5bee8734979351520c46bf3453d84..fc015b452ebf6ff824d4cd20520cf927eed2f30e 100644 (file)
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -192,6 +192,21 @@ The following keys are defined:
        supported as defined in the RISC-V ISA manual starting from commit
        d8ab5c78c207 ("Zihintpause is ratified").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index dda76a05420b1b0cb6fdbd1308521019f25dfdd4..7b95fadbea2a725d1b4f690e4862afff8c65e8ab 100644 (file)
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -60,6 +60,11 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZACAS         (1ULL << 34)
 #define                RISCV_HWPROBE_EXT_ZICOND        (1ULL << 35)
 #define                RISCV_HWPROBE_EXT_ZIHINTPAUSE   (1ULL << 36)
+#define                RISCV_HWPROBE_EXT_ZVE32X        (1ULL << 37)
+#define                RISCV_HWPROBE_EXT_ZVE32F        (1ULL << 38)
+#define                RISCV_HWPROBE_EXT_ZVE64X        (1ULL << 39)
+#define                RISCV_HWPROBE_EXT_ZVE64F        (1ULL << 40)
+#define                RISCV_HWPROBE_EXT_ZVE64D        (1ULL << 41)
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 969ef3d59dbe0098b91e614cf771a0df9d5e1421..35390b4a5a17291f2cd2882e25dc855f9aab5ec3 100644 (file)
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -114,6 +114,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZIHINTPAUSE);
 
                if (has_vector()) {
+                       EXT_KEY(ZVE32X);
+                       EXT_KEY(ZVE32F);
+                       EXT_KEY(ZVE64X);
+                       EXT_KEY(ZVE64F);
+                       EXT_KEY(ZVE64D);
                        EXT_KEY(ZVBB);
                        EXT_KEY(ZVBC);
                        EXT_KEY(ZVKB);