MIPS: uasm: Add drotr32 and uasm_i_drotr_safe.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: wim@iguana.be
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1495/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 697e40c06497bd62d8627b6171f43faf22ccfac8..3964b2e6c7d60d7fd512ed243a5b182d78a6c96c 100644 (file)
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -71,6 +71,7 @@ Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
 Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
@@ -176,6 +177,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
                uasm_i_dsrl32(p, a1, a2, a3 - 32);
 }
 
+static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+       if (a3 < 32)
+               uasm_i_drotr(p, a1, a2, a3);
+       else
+               uasm_i_drotr32(p, a1, a2, a3 - 32);
+}
+
 static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
                                    unsigned int a2, unsigned int a3)
 {

diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 611d564fdcf1e1bb4cbad07244ee2ca34192582c..fe041d5bb41ad0689a3d8e49c8657f83dd807ad7 100644 (file)
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -62,11 +62,12 @@ enum opcode {
        insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
        insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
        insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-       insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
-       insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
-       insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
-       insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
-       insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
+       insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
+       insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
+       insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
+       insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
+       insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
+       insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
        insn_dins, insn_syscall
 };
 
@@ -108,6 +109,7 @@ static struct insn insn_table[] __cpuinitdata = {
        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
        { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
+       { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
        { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
        { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
@@ -375,6 +377,7 @@ I_u2u1u3(_dsra)
 I_u2u1u3(_dsrl)
 I_u2u1u3(_dsrl32)
 I_u2u1u3(_drotr)
+I_u2u1u3(_drotr32)
 I_u3u1u2(_dsubu)
 I_0(_eret)
 I_u1(_j)