drm/amdgpu: remove hardcoded queue_mask in PACKET3_SET_RESOURCES

The assumption that we are only using the first pipe no longer holds.
Instead, calculate the queue_mask from the queue_bitmap.

Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 65c45ae67157daafd9af3a585dcdd5a5400ed4c7..bd0b2310f1d92f1b25a9418d49aa359c4bf7eb24 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4734,8 +4734,24 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
 {
        struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
        uint32_t scratch, tmp = 0;
+       uint64_t queue_mask = 0;
        int r, i;
 
+       for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
+               if (!test_bit(i, adev->gfx.mec.queue_bitmap))
+                       continue;
+
+               /* This situation may be hit in the future if a new HW
+                * generation exposes more than 64 queues. If so, the
+                * definition of queue_mask needs updating */
+               if (WARN_ON(i > (sizeof(queue_mask)*8))) {
+                       DRM_ERROR("Invalid KCQ enabled: %d\n", i);
+                       break;
+               }
+
+               queue_mask |= (1ull << i);
+       }
+
        r = amdgpu_gfx_scratch_get(adev, &scratch);
        if (r) {
                DRM_ERROR("Failed to get scratch reg (%d).\n", r);
@@ -4752,8 +4768,8 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
        /* set resources */
        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
        amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
-       amdgpu_ring_write(kiq_ring, 0x000000FF);        /* queue mask lo */
-       amdgpu_ring_write(kiq_ring, 0); /* queue mask hi */
+       amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
+       amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
        amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
        amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
        amdgpu_ring_write(kiq_ring, 0); /* oac mask */

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index db1d50e45985663c6e12446c95a03eaefc51c646..155a13911023d76d898de64686365f3cbdcf3f8f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2608,8 +2608,24 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
 {
        struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
        uint32_t scratch, tmp = 0;
+       uint64_t queue_mask = 0;
        int r, i;
 
+       for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
+               if (!test_bit(i, adev->gfx.mec.queue_bitmap))
+                       continue;
+
+               /* This situation may be hit in the future if a new HW
+                * generation exposes more than 64 queues. If so, the
+                * definition of queue_mask needs updating */
+               if (WARN_ON(i > (sizeof(queue_mask)*8))) {
+                       DRM_ERROR("Invalid KCQ enabled: %d\n", i);
+                       break;
+               }
+
+               queue_mask |= (1ull << i);
+       }
+
        r = amdgpu_gfx_scratch_get(adev, &scratch);
        if (r) {
                DRM_ERROR("Failed to get scratch reg (%d).\n", r);
@@ -2628,8 +2644,8 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
        amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
                          PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
-       amdgpu_ring_write(kiq_ring, 0x000000FF);        /* queue mask lo */
-       amdgpu_ring_write(kiq_ring, 0); /* queue mask hi */
+       amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
+       amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
        amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
        amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
        amdgpu_ring_write(kiq_ring, 0); /* oac mask */