wifi: mt76: mt7996: adjust WFDMA settings to improve performance

Refactor and update dma prefetch parts and also split band 1 traffic to
PCIe 1 to enhance throughput.

Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/dma.c b/drivers/net/wireless/mediatek/mt76/mt7996/dma.c
index 8bc08d993085387cecde0a3fd018d1dc8fd10643..7ec6c64b3fd1ce766323e9f7f395ecbc247979e2 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/mt7996/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/dma.c
@@ -99,38 +99,49 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
        MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7996_TXQ_FWDL);
 }
 
+static u32 __mt7996_dma_prefetch_base(u16 *base, u8 depth)
+{
+       u32 ret = *base << 16 | depth;
+
+       *base = *base + (depth << 4);
+
+       return ret;
+}
+
 static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
 {
-#define PREFETCH(_base, _depth)        ((_base) << 16 | (_depth))
+       u16 base = 0;
+
+#define PREFETCH(_depth)       (__mt7996_dma_prefetch_base(&base, (_depth)))
        /* prefetch SRAM wrapping boundary for tx/rx ring. */
-       mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2));
-       mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2));
-       mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4));
-       mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4));
-       mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2));
-       mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4));
-       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2));
-       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2));
-       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2));
-       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2));
-       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10));
-       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10));
+       mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x8));
+       mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x8));
+       mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0x8));
+       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x2));
+       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10));
+       mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x10));
 
        if (dev->has_rro) {
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND0) + ofs,
-                       PREFETCH(0x3a0, 0x10));
+                       PREFETCH(0x10));
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND2) + ofs,
-                       PREFETCH(0x4a0, 0x10));
+                       PREFETCH(0x10));
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND0) + ofs,
-                       PREFETCH(0x5a0, 0x4));
+                       PREFETCH(0x4));
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND1) + ofs,
-                       PREFETCH(0x5e0, 0x4));
+                       PREFETCH(0x4));
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND2) + ofs,
-                       PREFETCH(0x620, 0x4));
+                       PREFETCH(0x4));
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_TXFREE_BAND0) + ofs,
-                       PREFETCH(0x660, 0x4));
+                       PREFETCH(0x4));
                mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_TXFREE_BAND2) + ofs,
-                       PREFETCH(0x6a0, 0x4));
+                       PREFETCH(0x4));
        }
 #undef PREFETCH
 
@@ -295,6 +306,12 @@ static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset)
        mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1,
                 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE);
 
+       /* WFDMA rx threshold */
+       mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH, 0xc000c);
+       mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH, 0x10008);
+       mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH, 0x10008);
+       mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH, 0x20);
+
        if (dev->hif2) {
                /* GLO_CFG_EXT0 */
                mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
@@ -306,7 +323,18 @@ static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset)
                         WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE);
 
                mt76_set(dev, MT_WFDMA_HOST_CONFIG,
-                        MT_WFDMA_HOST_CONFIG_PDMA_BAND);
+                        MT_WFDMA_HOST_CONFIG_PDMA_BAND |
+                        MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
+
+               /* AXI read outstanding number */
+               mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL,
+                        MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14);
+
+               /* WFDMA rx threshold */
+               mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c);
+               mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH + hif1_ofs, 0x10008);
+               mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH + hif1_ofs, 0x10008);
+               mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH + hif1_ofs, 0x20);
        }
 
        if (dev->hif2) {

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/regs.h b/drivers/net/wireless/mediatek/mt76/mt7996/regs.h
index e9edba830aff32494570b15dfa46856a46a8f8c4..6102df912741f955ed7ed06f60bfa2515bf1cffe 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/mt7996/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/regs.h
@@ -379,6 +379,11 @@ enum base_rev {
 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO         BIT(27)
 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2   BIT(21)
 
+#define MT_WFDMA0_PAUSE_RX_Q_45_TH             MT_WFDMA0(0x268)
+#define MT_WFDMA0_PAUSE_RX_Q_67_TH             MT_WFDMA0(0x26c)
+#define MT_WFDMA0_PAUSE_RX_Q_89_TH             MT_WFDMA0(0x270)
+#define MT_WFDMA0_PAUSE_RX_Q_RRO_TH            MT_WFDMA0(0x27c)
+
 #define WF_WFDMA0_GLO_CFG_EXT0                 MT_WFDMA0(0x2b0)
 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD       BIT(18)
 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE  BIT(14)
@@ -401,10 +406,14 @@ enum base_rev {
 
 #define MT_WFDMA_HOST_CONFIG                   MT_WFDMA_EXT_CSR(0x30)
 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND         BIT(0)
+#define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1       BIT(22)
 
 #define MT_WFDMA_EXT_CSR_HIF_MISC              MT_WFDMA_EXT_CSR(0x44)
 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY         BIT(0)
 
+#define MT_WFDMA_AXI_R2A_CTRL                  MT_WFDMA_EXT_CSR(0x500)
+#define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK    GENMASK(4, 0)
+
 #define MT_PCIE_RECOG_ID                       0xd7090
 #define MT_PCIE_RECOG_ID_MASK                  GENMASK(30, 0)
 #define MT_PCIE_RECOG_ID_SEM                   BIT(31)