epp = cpu_data->epp_default;
 
        if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
-               u64 value;
-
-               ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
-               if (ret)
-                       return ret;
+               /*
+                * Use the cached HWP Request MSR value, because the register
+                * itself may be updated by intel_pstate_hwp_boost_up() or
+                * intel_pstate_hwp_boost_down() at any time.
+                */
+               u64 value = READ_ONCE(cpu_data->hwp_req_cached);
 
                value &= ~GENMASK_ULL(31, 24);
 
                        epp = epp_values[pref_index - 1];
 
                value |= (u64)epp << 24;
+               /*
+                * The only other updater of hwp_req_cached in the active mode,
+                * intel_pstate_hwp_set(), is called under the same lock as this
+                * function, so it cannot run in parallel with the update below.
+                */
+               WRITE_ONCE(cpu_data->hwp_req_cached, value);
                ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
        } else {
                if (epp == -EINVAL)