* - see sec. 4.12 of MPC8245 UM
*------------------------------------------------------------------*/
-// MCCR1
+/* MCCR1 */
#define CFG_ROMNAL 0
#define CFG_ROMFAL 2 /* (tacc=70ns)*mem_freq - 2 */
#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
/*--------------------------------------------------------------------
* 4.8 - Error Handling Registers
*------------------------------------------------------------------*/
-#define CFG_ERRENR1 0x11 // enable SDRAM refresh overflow error
+#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
/* SDRAM 0-256 MB */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)