/* LAN connected device generates an interrupt */
 #define E1000_ICR_PHYINT        0x00001000
 #define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
+#define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
 
 /* Extended Interrupt Cause Read */
 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
     E1000_IMS_TXDW   |    \
     E1000_IMS_RXDMT0 |    \
     E1000_IMS_RXSEQ  |    \
-    E1000_IMS_LSC)
+    E1000_IMS_LSC    |    \
+    E1000_IMS_DOUTSYNC)
 
 /* Interrupt Mask Set */
 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 
 /* Extended Interrupt Mask Set */
 #define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 /* Interrupt Cause Set */
 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 
 /* Extended Interrupt Cause Set */
 
 
        { "rx_long_byte_count", IGB_STAT(stats.gorc) },
        { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
        { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
+       { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
        { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
        { "tx_smbus", IGB_STAT(stats.mgptc) },
        { "rx_smbus", IGB_STAT(stats.mgprc) },
 
                wr32(E1000_EIAC, adapter->eims_enable_mask);
                wr32(E1000_EIAM, adapter->eims_enable_mask);
                wr32(E1000_EIMS, adapter->eims_enable_mask);
-               wr32(E1000_IMS, E1000_IMS_LSC);
+               wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
        } else {
                wr32(E1000_IMS, IMS_ENABLE_MASK);
                wr32(E1000_IAM, IMS_ENABLE_MASK);
        u32 icr = rd32(E1000_ICR);
 
        /* reading ICR causes bit 31 of EICR to be cleared */
+
+       if(icr & E1000_ICR_DOUTSYNC) {
+               /* HW is reporting DMA is out of sync */
+               adapter->stats.doosync++;
+       }
        if (!(icr & E1000_ICR_LSC))
                goto no_link_interrupt;
        hw->mac.get_link_status = 1;
                mod_timer(&adapter->watchdog_timer, jiffies + 1);
        
 no_link_interrupt:
-       wr32(E1000_IMS, E1000_IMS_LSC);
+       wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
        wr32(E1000_EIMS, adapter->eims_other);
 
        return IRQ_HANDLED;
 
        igb_write_itr(adapter->rx_ring);
 
+       if(icr & E1000_ICR_DOUTSYNC) {
+               /* HW is reporting DMA is out of sync */
+               adapter->stats.doosync++;
+       }
+
        if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
                hw->mac.get_link_status = 1;
                if (!test_bit(__IGB_DOWN, &adapter->state))
        if (!(icr & E1000_ICR_INT_ASSERTED))
                return IRQ_NONE;
 
+       if(icr & E1000_ICR_DOUTSYNC) {
+               /* HW is reporting DMA is out of sync */
+               adapter->stats.doosync++;
+       }
+
        eicr = rd32(E1000_EICR);
 
        if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {