spi: mediatek: support tick_delay without enhance_timing

commit 03b1be379dcee2e9c866c2a455a1a4a9581b3efd upstream.

this patch support tick_delay bit[31:30] without enhance_timing feature.

Fixes: f84d866ab43f("spi: mediatek: add tick_delay support")
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220315032411.2826-2-leilk.liu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 753bd313e6fdaaabe4063fc068e84d8d05b42983..2ca19b01948a2b51180e35aceb0ac302b1c5b59b 100644 (file)
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -43,8 +43,11 @@
 #define SPI_CFG1_PACKET_LOOP_OFFSET       8
 #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
 #define SPI_CFG1_GET_TICK_DLY_OFFSET      29
+#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1   30
 
 #define SPI_CFG1_GET_TICK_DLY_MASK        0xe0000000
+#define SPI_CFG1_GET_TICK_DLY_MASK_V1     0xc0000000
+
 #define SPI_CFG1_CS_IDLE_MASK             0xff
 #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
 #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
@@ -346,9 +349,15 @@ static int mtk_spi_prepare_message(struct spi_master *master,
 
        /* tick delay */
        reg_val = readl(mdata->base + SPI_CFG1_REG);
-       reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-       reg_val |= ((chip_config->tick_delay & 0x7)
-               << SPI_CFG1_GET_TICK_DLY_OFFSET);
+       if (mdata->dev_comp->enhance_timing) {
+               reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
+               reg_val |= ((chip_config->tick_delay & 0x7)
+                           << SPI_CFG1_GET_TICK_DLY_OFFSET);
+       } else {
+               reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
+               reg_val |= ((chip_config->tick_delay & 0x3)
+                           << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
+       }
        writel(reg_val, mdata->base + SPI_CFG1_REG);
 
        /* set hw cs timing */